-- TestBench Template LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY bch_fd IS END bch_fd; ARCHITECTURE behavior OF bch_fd IS -- Component Declaration COMPONENT fifodriver PORT( clk: in std_logic; rst: in std_logic; readreq: in std_logic; writereq: in std_logic; din: IN std_logic_VECTOR(7 downto 0); dout: OUT std_logic_VECTOR(7 downto 0); dready: out std_logic; full: OUT std_logic; empty: OUT std_logic; data_count: OUT std_logic_VECTOR(1 downto 0) ); END COMPONENT; signal clk:std_logic:='0'; signal rst:std_logic; signal readreq:std_logic:='0'; signal writereq:std_logic:='0'; signal din: std_logic_VECTOR(7 downto 0):="01010101"; signal dout: std_logic_VECTOR(7 downto 0); signal dready: std_logic; signal full: std_logic; signal empty: std_logic; signal data_count: std_logic_VECTOR(1 downto 0); BEGIN uut: fifodriver PORT MAP( clk => clk, rst => rst, readreq => readreq, writereq => writereq, din => din, dout => dout, dready => dready, full => full, empty => empty, data_count => data_count ); din <= std_logic_vector(unsigned(din) + 1) after 400 ns; rst<='1' , '0' after 510 ns; clk <= not clk after 25 ns; writereq <= not writereq after 700 ns; readreq <= not readreq after 900 ns; END;