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JDF G
// Created by Project Navigator ver 1.0
PROJECT clockgene
DESIGN clockgene
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s200
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
STIMULUS ..\portserie\bch_txserie.vhd
SOURCE ..\..\modele\nono_const.vhd
SOURCE ..\portserie\clockgene.vhd
[STRATEGY-LIST]
Normal=True