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authorprot2004-03-15 00:01:41 +0000
committerprot2004-03-15 00:01:41 +0000
commit2698ec1d2251323bdcc992295179c76b4686ab1e (patch)
treece32dc7dba65ea73f23734da09cf55f112774a6f /2004/n/fpga/src/portserie/clockgene/clockgene.npl
parent996c7b9bc5863e839f7352ee7fe3ca0be8dca944 (diff)
Le clock gen qui gère maintenant les 4 baudrates
Diffstat (limited to '2004/n/fpga/src/portserie/clockgene/clockgene.npl')
-rw-r--r--2004/n/fpga/src/portserie/clockgene/clockgene.npl25
1 files changed, 25 insertions, 0 deletions
diff --git a/2004/n/fpga/src/portserie/clockgene/clockgene.npl b/2004/n/fpga/src/portserie/clockgene/clockgene.npl
new file mode 100644
index 0000000..c7ab4ea
--- /dev/null
+++ b/2004/n/fpga/src/portserie/clockgene/clockgene.npl
@@ -0,0 +1,25 @@
+JDF G
+// Created by Project Navigator ver 1.0
+PROJECT clockgene
+DESIGN clockgene
+DEVFAM spartan2
+DEVFAMTIME 0
+DEVICE xc2s200
+DEVICETIME 0
+DEVPKG pq208
+DEVPKGTIME 0
+DEVSPEED -6
+DEVSPEEDTIME 0
+DEVTOPLEVELMODULETYPE HDL
+TOPLEVELMODULETYPETIME 0
+DEVSYNTHESISTOOL XST (VHDL/Verilog)
+SYNTHESISTOOLTIME 0
+DEVSIMULATOR Modelsim
+SIMULATORTIME 0
+DEVGENERATEDSIMULATIONMODEL VHDL
+GENERATEDSIMULATIONMODELTIME 0
+STIMULUS ..\portserie\bch_txserie.vhd
+SOURCE ..\..\modele\nono_const.vhd
+SOURCE ..\portserie\clockgene.vhd
+[STRATEGY-LIST]
+Normal=True