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authorprot2004-02-24 20:11:34 +0000
committerprot2004-02-24 20:11:34 +0000
commit513b74008aa84ec83bc62e242d2ed75ea9444564 (patch)
tree5b7adb2631a2faf75b3ae368ef31c597808a1719 /2004
parent737a773308c58c99768b36d8facf355df6f2b14c (diff)
On repasse en std_logic...
Snif
Diffstat (limited to '2004')
-rw-r--r--2004/n/fpga/src/portserie/bch_modele.vhd65
-rw-r--r--2004/n/fpga/src/portserie/decoder.vhd4
-rw-r--r--2004/n/fpga/src/portserie/fifo.vhd23
-rw-r--r--2004/n/fpga/src/portserie/isa_const.vhd27
-rw-r--r--2004/n/fpga/src/portserie/modele.vhd40
-rw-r--r--2004/n/fpga/src/portserie/nono_const.vhd52
-rw-r--r--2004/n/fpga/src/portserie/pack_compo.vhd77
-rw-r--r--2004/n/fpga/src/portserie/rxserie.vhd28
-rw-r--r--2004/n/fpga/src/portserie/txserie.vhd41
9 files changed, 50 insertions, 307 deletions
diff --git a/2004/n/fpga/src/portserie/bch_modele.vhd b/2004/n/fpga/src/portserie/bch_modele.vhd
deleted file mode 100644
index 18bc9a7..0000000
--- a/2004/n/fpga/src/portserie/bch_modele.vhd
+++ /dev/null
@@ -1,65 +0,0 @@
--- modele.vhd
--- Eurobot 2004 : APB Team
--- Auteur : Pierre-André Galmes
--- Fichier modèle pour la déclaration de module.
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-use work.nono_const.all;
-
-
-entity bch_modele is
-end bch_modele;
-
-architecture sim1 of bch_modele is
-
- component modele
- generic (
- -- adresses des différents registres du module.
- A_REG1 : T_ADDRESS := A_REG_IO_DIRECTION;
- A_REG2 : T_ADDRESS := A_REG_IO_DATA;
- A_REG3 : T_ADDRESS := A_REG_IO_INTERRUPT_MASK
- -- si autre choses à déclarer...
- );
- port (
- rst : in std_logic;
- clk : in std_logic;
- rw : in std_logic; -- read / write
- bus_data : inout unsigned ((NB_BIT_DATA - 1) downto 0);
- bus_address : in unsigned ((NB_BIT_ADDRESS - 1) downto 0)
- );
- end component;
-
- -- définiton des signaux
- signal rst : std_logic;
- signal clk : std_logic := '0';
- signal rw : std_logic; -- read / write
- signal bus_data : unsigned ((NB_BIT_DATA - 1) downto 0);
- signal bus_address : unsigned ((NB_BIT_ADDRESS - 1) downto 0);
-
-begin
- U1 : modele port map (
- rst => rst,
- clk => clk,
- rw => rw,
- bus_data => bus_data,
- bus_address => bus_address
- );
-
- rst <= '1', '0' after CK_PERIOD;
- clk <= not clk after (CK_PERIOD/2);
- rw <= '0';
- bus_address <= A_REG_IO_DIRECTION,
- A_REG_IO_DATA after 3*CK_PERIOD,
- A_REG_IO_INTERRUPT_MASK after 5*CK_PERIOD;
-end sim1;
-
-configuration cf1_bch_modele of bch_modele is
- for sim1
- for all : modele use entity work.modele(test_modele); end for;
- end for;
-end cf1_bch_modele;
-
diff --git a/2004/n/fpga/src/portserie/decoder.vhd b/2004/n/fpga/src/portserie/decoder.vhd
index 5f5afa0..219f308 100644
--- a/2004/n/fpga/src/portserie/decoder.vhd
+++ b/2004/n/fpga/src/portserie/decoder.vhd
@@ -11,9 +11,9 @@ use ieee.std_logic_unsigned.all;
use work.nono_const.all;
entity decoder is
- generic(adr : unsigned);
+ generic(adr : T_ADDRESS);
port(
- bus_address: in unsigned((NB_BIT_ADDRESS - 1) downto 0);
+ bus_address : in T_ADDRESS
cs: out std_logic
);
end decoder;
diff --git a/2004/n/fpga/src/portserie/fifo.vhd b/2004/n/fpga/src/portserie/fifo.vhd
index 35ad154..79303f4 100644
--- a/2004/n/fpga/src/portserie/fifo.vhd
+++ b/2004/n/fpga/src/portserie/fifo.vhd
@@ -13,8 +13,8 @@ use work.nono_const.all;
entity fifo is
port(
- data_in: in unsigned(7 downto 0);
- data_out: out unsigned(7 downto 0);
+ data_in: in T_DATA;
+ data_out: out T_ADDRESS;
ck: in std_logic;
ck_in: in std_logic;
ck_out: in std_logic;
@@ -48,9 +48,9 @@ end component;
-- en std_logic_vector :
-signal data_in_s: std_logic_vector(7 downto 0);
-signal data_input: unsigned(7 downto 0);
-signal data_out_s: std_logic_vector(7 downto 0);
+--signal data_in: std_logic_vector(7 downto 0);
+--signal data_input: std_logic_vector(7 downto 0);
+--signal data_out: std_logic_vector(7 downto 0);
-- autres signaux
signal read_enable:std_logic;
@@ -60,20 +60,23 @@ signal clock_fifo:std_logic;
begin
-- conversion de types :
---data_in_s <= TO_STDLOGICVECTOR(unsigned(data_in),8);
+--data_in_s <= TO_STDLOGICVECTOR(std_logic_vector(data_in),8);
--data_in_s <= conv_std_logic_vector(data_input);
-data_in_s <= conv_std_logic_vector(unsigned(data_input),data_input'length);
-data_out <= conv_unsigned(CONV_INTEGER(data_out_s),8);
+--data_in_s <= conv_std_logic_vector(unsigned(data_input),data_input'length);
+--data_out <= conv_unsigned(CONV_INTEGER(data_out_s),8);
+
+
+
FIFO1:fifoctlr_cc
port map(
clock_in=>clock_fifo,
read_enable_in=>read_enable,
write_enable_in=>write_enable,
- write_data_in=>data_in_s,
+ write_data_in=>data_in,
fifo_gsr_in=>purge,
- read_data_out=>data_out_s,
+ read_data_out=>data_out,
full_out=>flags(5),
empty_out=>flags(4),
fifocount_out=>flags(3 downto 0)
diff --git a/2004/n/fpga/src/portserie/isa_const.vhd b/2004/n/fpga/src/portserie/isa_const.vhd
deleted file mode 100644
index 12ab384..0000000
--- a/2004/n/fpga/src/portserie/isa_const.vhd
+++ /dev/null
@@ -1,27 +0,0 @@
--- isa_const.vhd
--- Eurobot 2004 : APB Team
--- Auteur : Pierre-André Galmes
--- Fichier de déclaration de constantes.
-
--- RQ : pour une indentation bien sous vim :
--- 1 - ":set shiftwidth=4"
--- 2 - se placer sous "package nono_const is"
--- 3 - tapez : = puis shift+G
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-
--- Constantes relatives au bus ISA
-package isa_const is
-
- -- Temps d'une période d'horloge sur le bus ISA
- constant ISA_CK_PERIOD : time := 50 ns;
-
- -- Ligne RW : lecture et écriture
- constant ISA_READ : std_logic := '0';
- constant ISA_WRITE : std_logic := '1';
-end isa_const;
-
diff --git a/2004/n/fpga/src/portserie/modele.vhd b/2004/n/fpga/src/portserie/modele.vhd
index 6a01686..a9f700b 100644
--- a/2004/n/fpga/src/portserie/modele.vhd
+++ b/2004/n/fpga/src/portserie/modele.vhd
@@ -1,15 +1,3 @@
--- modele.vhd
--- Eurobot 2004 : APB Team
--- Auteur : Pierre-André Galmes
--- Fichier modèle pour la déclaration de module.
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-use work.nono_const.all;
-
entity modele is
generic (
-- adresses des différents registres du module.
@@ -21,31 +9,7 @@ entity modele is
port (
rst : in std_logic;
clk : in std_logic;
- -- XXX : savoir si read = 0 ou 1 !!
rw : in std_logic; -- read (0) / write (1)
- bus_data : inout unsigned ((NB_BIT_DATA - 1) downto 0);
- bus_address : in unsigned ((NB_BIT_ADDRESS - 1) downto 0)
- masterck : in std_logic;
-
- );
-end entity;
+ bus_data : inout T_DATA;
+ bus_address : in T_ADDRESS
-architecture test_modele of modele is
-begin
- process (rst, clk)
- begin
- if (rst = '1') then
- bus_data <= x"00";
- elsif (clk'event and clk = '1') then
- if (bus_address = A_REG1) then
- bus_data <= x"01";
- else
- if (bus_address = A_REG2) then
- bus_data <= x"02";
- elsif (bus_address = A_REG3) then
- bus_data <= x"03";
- end if;
- end if;
- end if;
- end process;
-end test_modele;
diff --git a/2004/n/fpga/src/portserie/nono_const.vhd b/2004/n/fpga/src/portserie/nono_const.vhd
deleted file mode 100644
index 5c2e04a..0000000
--- a/2004/n/fpga/src/portserie/nono_const.vhd
+++ /dev/null
@@ -1,52 +0,0 @@
--- nono_const.vhd
--- Eurobot 2004 : APB Team
--- Auteur : Pierre-André Galmes
--- Fichier de déclaration de constantes.
-
--- RQ : pour une indentation bien sous vim :
--- 1 - ":set shiftwidth=4"
--- 2 - se placer sous "package nono_const is"
--- 3 - tapez : = puis shift+G
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-package nono_const is
-
- -- Temps d'une période d'horloge
- constant CK_PERIOD : time := 10 ns;
-
- -- Taille d'une addresse sur la carte
- -- RQ : 10 = nb suffisant
- -- 12 = 3 digit en héxa
- constant NB_BIT_ADDRESS : integer := 10;
-
- -- Taille des données sur la carte
- constant NB_BIT_DATA : integer := 8;
-
- -- Définition d'un nouveau type : ADDRESS
- subtype T_ADDRESS is unsigned ((NB_BIT_ADDRESS - 1) downto 0);
-
- -- Les différentes banques d'adresses (4 x 256)
- -- Rq pour Pierre : ça va influer sur le bloc de gestion du bus
- constant START_ADDR_B0 : T_ADDRESS := "0000000000";
- constant START_ADDR_B1 : T_ADDRESS := "0100000000";
- constant START_ADDR_B2 : T_ADDRESS := "1000000000";
- constant START_ADDR_B3 : T_ADDRESS := "1100000000";
-
- -- Les addresses des différents registres.
-
- -- gestion des interruptions
- constant A_INTERRUPT_MANAGER : T_ADDRESS := START_ADDR_B0 + x"00";
- -- Bloc d'IO
- constant A_REG_IO_DIRECTION : T_ADDRESS := START_ADDR_B0 + x"01";
- constant A_REG_IO_DATA : T_ADDRESS := START_ADDR_B0 + x"02";
- constant A_REG_IO_INTERRUPT_MASK : T_ADDRESS := START_ADDR_B0 + x"03";
- -- Bloc port série
- -- Bloc caméra
- -- Bloc PWM
- -- Bloc I²C
- -- Bloc servo-moteurs
-end nono_const;
diff --git a/2004/n/fpga/src/portserie/pack_compo.vhd b/2004/n/fpga/src/portserie/pack_compo.vhd
deleted file mode 100644
index fe14b98..0000000
--- a/2004/n/fpga/src/portserie/pack_compo.vhd
+++ /dev/null
@@ -1,77 +0,0 @@
--- fifodriver.vhd
--- Eurobot 2004 : APB Team
--- Auteur : Pierre Prot
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-use work.nono_const.all;
-
--- pilote de fifo
-entity fifodriver is
- port(
- masterck,reset: in std_logic;
- readreq,writereq: in std_logic;
- fifock:out std_logic;
- fiforead,fifowrite:std_logic
- );
- constant PRESCAL := 16;
-end fifodriver;
-
-architecture rtl of fifodriver is
-signal subck: unsigned :=0;
-signal state_actual,state_next : integer;
-
-begin
--- la partie COMBI
- COMBI:process(state_actual,readreq,writereq)
- begin
- fifowrite <= '0';
- fiforead <= '0';
- fifock <= '0';
- state_next <= 1;
-
- case state_actual is
- when 1 => if (readreq='1') then
- state_next <= 2;
- elsif(writereq='1') then
- state_next <= 4;
- end if;
-
- when 2 => state_next <= 3;
- fiforead<='1';
-
- when 3 => state_next <= 1;
- fiforead<='1';
- fifock<='1';
-
- when 4 => state_next <= 5;
- fifowrite<='1';
-
- when 5 => state_next <= 1;
- fifowrite<='1';
- fifock<='1';
-
- when others => NULL;
- end case;
- end process COMBI;
-
--- la partie SEQU
- SEQU:process(masterck,reset)
- begin
- if (reset='1') then
- state_actual <= 1;
- elsif (masterck'event and masterck='1') then
- if(subck=PRESCAL) then
- subck<=0;
- state_actual <= state_next ;
- else
- subck<=subck+1;
- end if;
- end if;
- end process SEQU;
-end rtl;
-
-
diff --git a/2004/n/fpga/src/portserie/rxserie.vhd b/2004/n/fpga/src/portserie/rxserie.vhd
index c44536b..21c8080 100644
--- a/2004/n/fpga/src/portserie/rxserie.vhd
+++ b/2004/n/fpga/src/portserie/rxserie.vhd
@@ -32,18 +32,22 @@ library ieee;
library ieee.std_logic_1164.all;
entity rxserie is
-generic(adr : integer);
-constant adr_w : integer :=10;
-port(
- adrbus: in std_logic_vector((adr_w - 1) downto 0);
- databus: inout std_logic_vector(7 downto 0);
- rw: in std_logic;
- busck: in std_logic;
- rst: in std_logic;
- masterck: in std_logic;
- rxin: in std_logic;
- FNEIout: out std_logic;
- FFIout: out std_logic;
+ generic (
+ -- adresses des différents registres du module.
+ A_DATA : T_ADDRESS;
+ A_CONFIG : T_ADDRESS;
+ A_FLAG : T_ADDRESS
+ );
+ port (
+ rst : in std_logic;
+ clk : in std_logic;
+ rw : in std_logic; -- read (0) / write (1)
+ bus_data : inout T_DATA;
+ bus_address : in T_ADDRESS;
+ masterck: in std_logic;
+ rxin: in std_logic;
+ FNEIout: out std_logic;
+ FFIout: out std_logic
);
end rxserie;
diff --git a/2004/n/fpga/src/portserie/txserie.vhd b/2004/n/fpga/src/portserie/txserie.vhd
index 5995f9c..997a60d 100644
--- a/2004/n/fpga/src/portserie/txserie.vhd
+++ b/2004/n/fpga/src/portserie/txserie.vhd
@@ -46,10 +46,11 @@ entity txserie is
);
port (
rst : in std_logic;
- busclk : in std_logic;
+ clk : in std_logic;
rw : in std_logic; -- read (0) / write (1)
- bus_data : inout unsigned ((NB_BIT_DATA - 1) downto 0);
- bus_address : in unsigned ((NB_BIT_ADDRESS - 1) downto 0);
+ bus_data : inout T_DATA;
+ bus_address : in T_ADDRESS
+
masterck: in std_logic;
txout: out std_logic;
minIRQ: out std_logic
@@ -61,10 +62,10 @@ architecture rtl of txserie is
component registre
generic(adr : T_ADDRESS);
port(
- bus_address: in unsigned ((NB_BIT_ADDRESS - 1) downto 0);
- bus_data: inout unsigned(7 downto 0);
- input: in std_logic_vector(7 downto 0);
- output: out std_logic_vector(7 downto 0);
+ bus_address: in T_ADDRESS;
+ bus_data: inout T_DATA;
+ input: in T_DATA;
+ output: out T_DATA;
rw: in std_logic;
load: in std_logic;
ck: in std_logic;
@@ -75,8 +76,8 @@ end component;
component fifo is
port(
- data_in: in unsigned(7 downto 0);
- data_out: out unsigned(7 downto 0);
+ data_in: in T_DATA;
+ data_out: out T_DATA;
ck: in std_logic;
ck_in: in std_logic;
ck_out: in std_logic;
@@ -88,7 +89,7 @@ end component;
component transmitter
port(
- data_in: in unsigned(7 downto 0);
+ data_in: in T_DATA;
ck: in std_logic;
flag: out std_logic;
txout: out std_logic
@@ -106,7 +107,7 @@ end component;
component decoder
generic(adr : unsigned);
port(
- bus_address: in unsigned((NB_BIT_ADDRESS - 1) downto 0);
+ bus_address: in T_DATA;
cs: out std_logic
);
end component;
@@ -122,15 +123,11 @@ signal purge: std_logic;
signal geneck: std_logic;
signal txck: std_logic;
signal busck: std_logic;
---signal bus_address: std_logic_vector((NB_BIT_ADDRESS - 1) downto 0);
---signal bus_data: std_logic_vector(7 downto 0);
---signal rw: std_logic;
---signal rst: std_logic;
-signal confreg: unsigned(7 downto 0);
-signal flagreg: unsigned(7 downto 0);
+signal confreg: T_DATA;
+signal flagreg: T_DATA;
signal interflag: std_logic_vector(5 downto 0);
-signal datareg: unsigned(7 downto 0);
-signal inter_data: unsigned(7 downto 0);
+signal datareg: T_DATA;
+signal inter_data: T_DATA;
signal txempty: std_logic;
signal csFifo: std_logic;
signal fifockin: std_logic;
@@ -148,7 +145,7 @@ FIFO1: fifo
purge=>confreg(3)
);
-flagreg(5 downto 0)<=conv_unsigned(CONV_INTEGER(interflag),8);
+flagreg(5 downto 0)<=interflag;
fifockin<=csFifo and not rw and busck;
fifockout<=txempty; -- à vérifier !!! Cette ligne est valable pour
@@ -219,7 +216,3 @@ DECOD : decoder
end rtl;
-
-
-
-