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Diffstat (limited to '2004/n/fpga/src/portserie/fifo.vhd')
-rw-r--r--2004/n/fpga/src/portserie/fifo.vhd23
1 files changed, 13 insertions, 10 deletions
diff --git a/2004/n/fpga/src/portserie/fifo.vhd b/2004/n/fpga/src/portserie/fifo.vhd
index 35ad154..79303f4 100644
--- a/2004/n/fpga/src/portserie/fifo.vhd
+++ b/2004/n/fpga/src/portserie/fifo.vhd
@@ -13,8 +13,8 @@ use work.nono_const.all;
entity fifo is
port(
- data_in: in unsigned(7 downto 0);
- data_out: out unsigned(7 downto 0);
+ data_in: in T_DATA;
+ data_out: out T_ADDRESS;
ck: in std_logic;
ck_in: in std_logic;
ck_out: in std_logic;
@@ -48,9 +48,9 @@ end component;
-- en std_logic_vector :
-signal data_in_s: std_logic_vector(7 downto 0);
-signal data_input: unsigned(7 downto 0);
-signal data_out_s: std_logic_vector(7 downto 0);
+--signal data_in: std_logic_vector(7 downto 0);
+--signal data_input: std_logic_vector(7 downto 0);
+--signal data_out: std_logic_vector(7 downto 0);
-- autres signaux
signal read_enable:std_logic;
@@ -60,20 +60,23 @@ signal clock_fifo:std_logic;
begin
-- conversion de types :
---data_in_s <= TO_STDLOGICVECTOR(unsigned(data_in),8);
+--data_in_s <= TO_STDLOGICVECTOR(std_logic_vector(data_in),8);
--data_in_s <= conv_std_logic_vector(data_input);
-data_in_s <= conv_std_logic_vector(unsigned(data_input),data_input'length);
-data_out <= conv_unsigned(CONV_INTEGER(data_out_s),8);
+--data_in_s <= conv_std_logic_vector(unsigned(data_input),data_input'length);
+--data_out <= conv_unsigned(CONV_INTEGER(data_out_s),8);
+
+
+
FIFO1:fifoctlr_cc
port map(
clock_in=>clock_fifo,
read_enable_in=>read_enable,
write_enable_in=>write_enable,
- write_data_in=>data_in_s,
+ write_data_in=>data_in,
fifo_gsr_in=>purge,
- read_data_out=>data_out_s,
+ read_data_out=>data_out,
full_out=>flags(5),
empty_out=>flags(4),
fifocount_out=>flags(3 downto 0)