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authorprot2004-02-24 15:13:50 +0000
committerprot2004-02-24 15:13:50 +0000
commit1287e98de906f1f6a15f2cdc5762bba729a9dd81 (patch)
tree746689c0cffb43af3e97adae1e649612a8b9dee2 /2004
parentcf51db95b11529fcb2a848458745eed3f32612e5 (diff)
Conversions de type unsigned<->std_logic_vector
C'est chiant !
Diffstat (limited to '2004')
-rw-r--r--2004/n/fpga/src/portserie/fifo.vhd9
-rw-r--r--2004/n/fpga/src/portserie/txserie.vhd35
2 files changed, 22 insertions, 22 deletions
diff --git a/2004/n/fpga/src/portserie/fifo.vhd b/2004/n/fpga/src/portserie/fifo.vhd
index a238929..04ff690 100644
--- a/2004/n/fpga/src/portserie/fifo.vhd
+++ b/2004/n/fpga/src/portserie/fifo.vhd
@@ -49,6 +49,7 @@ end component;
-- en std_logic_vector :
signal data_in_s: std_logic_vector(7 downto 0);
+signal data_input: unsigned(7 downto 0);
signal data_out_s: std_logic_vector(7 downto 0);
-- autres signaux
@@ -59,10 +60,9 @@ signal clock_fifo:std_logic;
begin
-- conversion de types :
---data_in_s <= TO_STDLOGICVECTOR(std);
-data_in_s <= conv_std_logic_vector(data_in);
-
-data_out <= TO_UNSIGNED(bvtoi(data_out_s));
+--data_in_s <= TO_STDLOGICVECTOR(unsigned(data_in),8);
+data_out <= TO_UNSIGNED(CONV_INTEGER(data_out_s),8);
+data_in_s <= conv_std_logic_vector(data_input);
FIFO1:fifoctlr_cc
port map(
@@ -92,3 +92,4 @@ end rtl;
+
diff --git a/2004/n/fpga/src/portserie/txserie.vhd b/2004/n/fpga/src/portserie/txserie.vhd
index cad7dda..11e0946 100644
--- a/2004/n/fpga/src/portserie/txserie.vhd
+++ b/2004/n/fpga/src/portserie/txserie.vhd
@@ -72,20 +72,20 @@ component registre
);
end component;
-component fifo
+
+component fifo is
port(
- data_in: in unsigned(7 downto 0);
- data_out: in unsigned(7 downto 0);
- ck_in: in std_logic;
- ck_out: in std_logic;
- f0: out std_logic;
- f1: out std_logic;
- f2: out std_logic;
- f3: out std_logic;
+ data_in: in unsigned(7 downto 0);
+ data_out: out unsigned(7 downto 0);
+ ck: in std_logic;
+ ck_in: in std_logic;
+ ck_out: in std_logic;
+ flags: out std_logic_vector(5 downto 0);
purge: in std_logic
);
end component;
-
+
+
component transmitter
port(
data_in: in unsigned(7 downto 0);
@@ -126,9 +126,9 @@ signal busck: std_logic;
--signal bus_data: std_logic_vector(7 downto 0);
--signal rw: std_logic;
--signal rst: std_logic;
-signal confreg: std_logic_vector(7 downto 0);
-signal flagreg: std_logic_vector(7 downto 0);
-signal datareg: std_logic_vector(7 downto 0);
+signal confreg: unsigned(7 downto 0);
+signal flagreg: unsigned(7 downto 0);
+signal datareg: unsigned(7 downto 0);
signal inter_data: unsigned(7 downto 0);
signal txempty: std_logic;
signal csFifo: std_logic;
@@ -140,13 +140,11 @@ FIFO1: fifo
port map(
data_in=>bus_data,
data_out=>inter_data,
+ ck=>masterck,
ck_in=>fifockin,
ck_out=>fifockout,
- f0=>fifoEmpty,
- f1=>fifoLI0,
- f2=>fifoLI1,
- f3=>fifoFull,
- purge=>'1' --confreg(3 downto 3)
+ flags=>flagreg(5 downto 0),
+ purge=>confreg(3)
);
fifockin<=csFifo and not rw and busck;
@@ -219,3 +217,4 @@ end rtl;
+