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authorprot2004-02-24 13:09:54 +0000
committerprot2004-02-24 13:09:54 +0000
commitcf51db95b11529fcb2a848458745eed3f32612e5 (patch)
tree326535ed394fc3ab84d740502d8ab5f72c0ced30 /2004
parentbd04482c1a6feae7d057e1994006a28195282aef (diff)
cration de la fifo
Diffstat (limited to '2004')
-rw-r--r--2004/n/fpga/src/portserie/clockgene.vhd27
-rw-r--r--2004/n/fpga/src/portserie/decoder.vhd33
-rw-r--r--2004/n/fpga/src/portserie/fifo.vhd94
-rw-r--r--2004/n/fpga/src/portserie/fifodriver.vhd78
-rw-r--r--2004/n/fpga/src/portserie/pack_compo.vhd77
-rw-r--r--2004/n/fpga/src/portserie/txserie.vhd58
6 files changed, 341 insertions, 26 deletions
diff --git a/2004/n/fpga/src/portserie/clockgene.vhd b/2004/n/fpga/src/portserie/clockgene.vhd
new file mode 100644
index 0000000..2a13a8c
--- /dev/null
+++ b/2004/n/fpga/src/portserie/clockgene.vhd
@@ -0,0 +1,27 @@
+-- clockgene.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre Prot
+-- clock
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+use work.nono_const.all;
+
+-- horloge de ref
+entity clockgene is
+ port(
+ ckin: in std_logic;
+ ckout: out std_logic;
+ param: in std_logic_vector(1 downto 0)
+ );
+end clockgene;
+
+architecture rtl of clockgene is
+begin
+ ckout<=ckin;
+end rtl;
+
+
diff --git a/2004/n/fpga/src/portserie/decoder.vhd b/2004/n/fpga/src/portserie/decoder.vhd
new file mode 100644
index 0000000..5f5afa0
--- /dev/null
+++ b/2004/n/fpga/src/portserie/decoder.vhd
@@ -0,0 +1,33 @@
+-- decoder.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre Prot
+-- décodeur
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+use work.nono_const.all;
+
+entity decoder is
+ generic(adr : unsigned);
+ port(
+ bus_address: in unsigned((NB_BIT_ADDRESS - 1) downto 0);
+ cs: out std_logic
+ );
+end decoder;
+
+architecture rtl of decoder is
+begin
+process(bus_address)
+begin
+ if(bus_address=adr)
+ then
+ cs<='1';
+ else
+ cs<='0';
+ end if;
+end process;
+end rtl;
+
diff --git a/2004/n/fpga/src/portserie/fifo.vhd b/2004/n/fpga/src/portserie/fifo.vhd
new file mode 100644
index 0000000..a238929
--- /dev/null
+++ b/2004/n/fpga/src/portserie/fifo.vhd
@@ -0,0 +1,94 @@
+-- fifo.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre Prot
+-- fifo
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+use work.nono_const.all;
+
+entity fifo is
+ port(
+ data_in: in unsigned(7 downto 0);
+ data_out: out unsigned(7 downto 0);
+ ck: in std_logic;
+ ck_in: in std_logic;
+ ck_out: in std_logic;
+ flags: out std_logic_vector(5 downto 0);
+ purge: in std_logic
+ );
+end fifo;
+
+architecture rtl of fifo is
+component fifodriver is
+ port(
+ masterck,reset: in std_logic;
+ readreq,writereq: in std_logic;
+ fifock:out std_logic;
+ fiforead:out std_logic;
+ fifowrite:out std_logic
+ );
+end component;
+
+component fifoctlr_cc is
+ port (clock_in: IN std_logic;
+ read_enable_in: IN std_logic;
+ write_enable_in: IN std_logic;
+ write_data_in: IN std_logic_vector(7 downto 0);
+ fifo_gsr_in: IN std_logic;
+ read_data_out: OUT std_logic_vector(7 downto 0);
+ full_out: OUT std_logic;
+ empty_out: OUT std_logic;
+ fifocount_out: OUT std_logic_vector(3 downto 0));
+end component;
+
+
+-- en std_logic_vector :
+signal data_in_s: std_logic_vector(7 downto 0);
+signal data_out_s: std_logic_vector(7 downto 0);
+
+-- autres signaux
+signal read_enable:std_logic;
+signal write_enable:std_logic;
+signal clock_fifo:std_logic;
+
+
+begin
+-- conversion de types :
+--data_in_s <= TO_STDLOGICVECTOR(std);
+data_in_s <= conv_std_logic_vector(data_in);
+
+data_out <= TO_UNSIGNED(bvtoi(data_out_s));
+
+FIFO1:fifoctlr_cc
+ port map(
+ clock_in=>clock_fifo,
+ read_enable_in=>read_enable,
+ write_enable_in=>write_enable,
+ write_data_in=>data_in_s,
+ fifo_gsr_in=>purge,
+ read_data_out=>data_out_s,
+ full_out=>flags(5),
+ empty_out=>flags(4),
+ fifocount_out=>flags(3 downto 0)
+ );
+
+FD1:fifodriver
+ port map(
+ masterck=>ck,
+ reset=>purge,
+ readreq=>ck_out,
+ writereq=>ck_in,
+ fifock=>clock_fifo,
+ fiforead=>read_enable,
+ fifowrite=>write_enable
+ );
+
+end rtl;
+
+
+
diff --git a/2004/n/fpga/src/portserie/fifodriver.vhd b/2004/n/fpga/src/portserie/fifodriver.vhd
new file mode 100644
index 0000000..974871e
--- /dev/null
+++ b/2004/n/fpga/src/portserie/fifodriver.vhd
@@ -0,0 +1,78 @@
+-- fifodriver.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre Prot
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+use work.nono_const.all;
+
+-- pilote de fifo
+entity fifodriver is
+ port(
+ masterck,reset: in std_logic;
+ readreq,writereq: in std_logic;
+ fifock:out std_logic;
+ fiforead:out std_logic;
+ fifowrite:out std_logic
+ );
+ constant PRESCAL :integer:= 16;
+end fifodriver;
+
+architecture rtl of fifodriver is
+signal subck: integer :=0;
+signal state_actual,state_next : integer;
+
+begin
+-- la partie COMBI
+ COMBI:process(state_actual,readreq,writereq)
+ begin
+ fifowrite <= '0';
+ fiforead <= '0';
+ fifock <= '0';
+ state_next <= 1;
+
+ case state_actual is
+ when 1 => if (readreq='1') then
+ state_next <= 2;
+ elsif(writereq='1') then
+ state_next <= 4;
+ end if;
+
+ when 2 => state_next <= 3;
+ fiforead<='1';
+
+ when 3 => state_next <= 1;
+ fiforead<='1';
+ fifock<='1';
+
+ when 4 => state_next <= 5;
+ fifowrite<='1';
+
+ when 5 => state_next <= 1;
+ fifowrite<='1';
+ fifock<='1';
+
+ when others => NULL;
+ end case;
+ end process COMBI;
+
+-- la partie SEQU
+ SEQU:process(masterck,reset)
+ begin
+ if (reset='1') then
+ state_actual <= 1;
+ elsif (masterck'event and masterck='1') then
+ if(subck=PRESCAL) then
+ subck<=0;
+ state_actual <= state_next ;
+ else
+ subck<=subck+1;
+ end if;
+ end if;
+ end process SEQU;
+end rtl;
+
+
diff --git a/2004/n/fpga/src/portserie/pack_compo.vhd b/2004/n/fpga/src/portserie/pack_compo.vhd
new file mode 100644
index 0000000..fe14b98
--- /dev/null
+++ b/2004/n/fpga/src/portserie/pack_compo.vhd
@@ -0,0 +1,77 @@
+-- fifodriver.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre Prot
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+use work.nono_const.all;
+
+-- pilote de fifo
+entity fifodriver is
+ port(
+ masterck,reset: in std_logic;
+ readreq,writereq: in std_logic;
+ fifock:out std_logic;
+ fiforead,fifowrite:std_logic
+ );
+ constant PRESCAL := 16;
+end fifodriver;
+
+architecture rtl of fifodriver is
+signal subck: unsigned :=0;
+signal state_actual,state_next : integer;
+
+begin
+-- la partie COMBI
+ COMBI:process(state_actual,readreq,writereq)
+ begin
+ fifowrite <= '0';
+ fiforead <= '0';
+ fifock <= '0';
+ state_next <= 1;
+
+ case state_actual is
+ when 1 => if (readreq='1') then
+ state_next <= 2;
+ elsif(writereq='1') then
+ state_next <= 4;
+ end if;
+
+ when 2 => state_next <= 3;
+ fiforead<='1';
+
+ when 3 => state_next <= 1;
+ fiforead<='1';
+ fifock<='1';
+
+ when 4 => state_next <= 5;
+ fifowrite<='1';
+
+ when 5 => state_next <= 1;
+ fifowrite<='1';
+ fifock<='1';
+
+ when others => NULL;
+ end case;
+ end process COMBI;
+
+-- la partie SEQU
+ SEQU:process(masterck,reset)
+ begin
+ if (reset='1') then
+ state_actual <= 1;
+ elsif (masterck'event and masterck='1') then
+ if(subck=PRESCAL) then
+ subck<=0;
+ state_actual <= state_next ;
+ else
+ subck<=subck+1;
+ end if;
+ end if;
+ end process SEQU;
+end rtl;
+
+
diff --git a/2004/n/fpga/src/portserie/txserie.vhd b/2004/n/fpga/src/portserie/txserie.vhd
index df1ec41..cad7dda 100644
--- a/2004/n/fpga/src/portserie/txserie.vhd
+++ b/2004/n/fpga/src/portserie/txserie.vhd
@@ -49,19 +49,19 @@ entity txserie is
busclk : in std_logic;
rw : in std_logic; -- read (0) / write (1)
bus_data : inout unsigned ((NB_BIT_DATA - 1) downto 0);
- bus_address : in unsigned ((NB_BIT_ADDRESS - 1) downto 0)
- masterck: in std_logic;
+ bus_address : in unsigned ((NB_BIT_ADDRESS - 1) downto 0);
+ masterck: in std_logic;
txout: out std_logic;
- minIRQ: out std_logic;
+ minIRQ: out std_logic
);
end txserie;
architecture rtl of txserie is
component registre
- generic(adr : integer);
+ generic(adr : T_ADDRESS);
port(
- bus_address: in unsigned((NB_BIT_ADRESS - 1) downto 0);
+ bus_address: in unsigned ((NB_BIT_ADDRESS - 1) downto 0);
bus_data: inout unsigned(7 downto 0);
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0);
@@ -74,8 +74,8 @@ end component;
component fifo
port(
- data_in: in std_logic_vector(7 downto 0);
- data_out: in std_logic_vector(7 downto 0);
+ data_in: in unsigned(7 downto 0);
+ data_out: in unsigned(7 downto 0);
ck_in: in std_logic;
ck_out: in std_logic;
f0: out std_logic;
@@ -88,7 +88,7 @@ end component;
component transmitter
port(
- data_in: in std_logic_vector(7 downto 0);
+ data_in: in unsigned(7 downto 0);
ck: in std_logic;
flag: out std_logic;
txout: out std_logic
@@ -104,9 +104,9 @@ component clockgene
end component;
component decoder
- generic(adr : integer);
+ generic(adr : unsigned);
port(
- bus_address: in std_logic_vector((NB_BIT_ADRESS - 1) downto 0);
+ bus_address: in unsigned((NB_BIT_ADDRESS - 1) downto 0);
cs: out std_logic
);
end component;
@@ -122,27 +122,31 @@ signal purge: std_logic;
signal geneck: std_logic;
signal txck: std_logic;
signal busck: std_logic;
-signal bus_address: std_logic_vector((NB_BIT_ADRESS - 1) downto 0);
-signal bus_data: std_logic_vector(7 downto 0);
-signal rw: std_logic;
-signal rst: std_logic;
-signal txdata: std_logic;
+--signal bus_address: std_logic_vector((NB_BIT_ADDRESS - 1) downto 0);
+--signal bus_data: std_logic_vector(7 downto 0);
+--signal rw: std_logic;
+--signal rst: std_logic;
+signal confreg: std_logic_vector(7 downto 0);
+signal flagreg: std_logic_vector(7 downto 0);
+signal datareg: std_logic_vector(7 downto 0);
+signal inter_data: unsigned(7 downto 0);
signal txempty: std_logic;
signal csFifo: std_logic;
signal fifockin: std_logic;
signal fifockout: std_logic;
+begin
FIFO1: fifo
port map(
data_in=>bus_data,
- data_out=>txdata,
+ data_out=>inter_data,
ck_in=>fifockin,
- ck_out=>fifockout
+ ck_out=>fifockout,
f0=>fifoEmpty,
f1=>fifoLI0,
f2=>fifoLI1,
f3=>fifoFull,
- purge=>confreg(3)
+ purge=>'1' --confreg(3 downto 3)
);
fifockin<=csFifo and not rw and busck;
@@ -151,24 +155,25 @@ fifockout<=txempty; -- à vérifier !!! Cette ligne est valable pour
TX1 : transmitter
port map(
- data_in=>txdata,
+ data_in=>inter_data,
ck=>txck,
flag=>txempty,
- txout=>txout,
+ txout=>txout
);
CLOCK1 : clockgene
port map(
ck_in=>geneck,
ck_out=>txck,
- param=>confreg(1 downto 0)
+ param=>"11" --confreg(1 downto 0)
);
-geneck<=confreg(4) and masterck; -- On/Off et masterck
+
+geneck<='1'; --confreg(4) and masterck; -- On/Off et masterck
-- Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0)
RCONF : registre
- generic map(adr=>adr+1)
+ generic map(adr=>A_DATA)
port map(
bus_address=>bus_address,
bus_data=>bus_data,
@@ -182,7 +187,7 @@ RCONF : registre
-- Flag : (x ! x ! x ! x ! Empty ! Full/Int ! FLI1 ! FLI0)
RFLAG : registre
- generic map(adr=>adr+2)
+ generic map(adr=>A_FLAG)
port map(
bus_address=>bus_address,
bus_data=>bus_data,
@@ -202,10 +207,10 @@ flagreg(0)<=fifoLI0;
-- la sortie intout est active si la pile est pleine ET si le bit de conf est
-- activé
-intout<=fifoFull and confreg(2); -- IntEn et fifoFull
+minIRQ<=fifoFull and confreg(2); -- IntEn et fifoFull
DECOD : decoder
- generic map(adr=>adr)
+ generic map(adr=>A_DATA)
port map(
bus_address=>bus_address,
cs=>csFifo
@@ -213,3 +218,4 @@ DECOD : decoder
end rtl;
+