summaryrefslogtreecommitdiff
path: root/2004/n/fpga/src
diff options
context:
space:
mode:
authorprot2004-03-14 23:52:18 +0000
committerprot2004-03-14 23:52:18 +0000
commited85c54d3129c8c39327d07270f06edfd8538446 (patch)
tree0392dacea5280d18fb6872a0cf094753aa8364e8 /2004/n/fpga/src
parent733998a6a054548033ce3c76924590eb773c1b22 (diff)
sert à rien çui-là
Diffstat (limited to '2004/n/fpga/src')
-rw-r--r--2004/n/fpga/src/portserie/rxserie/sfifo.vhd119
1 files changed, 0 insertions, 119 deletions
diff --git a/2004/n/fpga/src/portserie/rxserie/sfifo.vhd b/2004/n/fpga/src/portserie/rxserie/sfifo.vhd
deleted file mode 100644
index 7455e8a..0000000
--- a/2004/n/fpga/src/portserie/rxserie/sfifo.vhd
+++ /dev/null
@@ -1,119 +0,0 @@
---------------------------------------------------------------------------------
--- This file is owned and controlled by Xilinx and must be used --
--- solely for design, simulation, implementation and creation of --
--- design files limited to Xilinx devices or technologies. Use --
--- with non-Xilinx devices or technologies is expressly prohibited --
--- and immediately terminates your license. --
--- --
--- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
--- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
--- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
--- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
--- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
--- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
--- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
--- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
--- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
--- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
--- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
--- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
--- FOR A PARTICULAR PURPOSE. --
--- --
--- Xilinx products are not intended for use in life support --
--- appliances, devices, or systems. Use in such applications are --
--- expressly prohibited. --
--- --
--- (c) Copyright 1995-2003 Xilinx, Inc. --
--- All rights reserved. --
---------------------------------------------------------------------------------
--- You must compile the wrapper file sfifo.vhd when simulating
--- the core, sfifo. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Guide".
-
--- The synopsys directives "translate_off/translate_on" specified
--- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
--- synthesis tools. Ensure they are correct for your synthesis tool(s).
-
--- synopsys translate_off
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-
-Library XilinxCoreLib;
-ENTITY sfifo IS
- port (
- clk: IN std_logic;
- sinit: IN std_logic;
- din: IN std_logic_VECTOR(7 downto 0);
- wr_en: IN std_logic;
- rd_en: IN std_logic;
- dout: OUT std_logic_VECTOR(7 downto 0);
- full: OUT std_logic;
- empty: OUT std_logic;
- rd_ack: OUT std_logic;
- wr_ack: OUT std_logic;
- rd_err: OUT std_logic;
- wr_err: OUT std_logic;
- data_count: OUT std_logic_VECTOR(1 downto 0));
-END sfifo;
-
-ARCHITECTURE sfifo_a OF sfifo IS
-
-component wrapped_sfifo
- port (
- clk: IN std_logic;
- sinit: IN std_logic;
- din: IN std_logic_VECTOR(7 downto 0);
- wr_en: IN std_logic;
- rd_en: IN std_logic;
- dout: OUT std_logic_VECTOR(7 downto 0);
- full: OUT std_logic;
- empty: OUT std_logic;
- rd_ack: OUT std_logic;
- wr_ack: OUT std_logic;
- rd_err: OUT std_logic;
- wr_err: OUT std_logic;
- data_count: OUT std_logic_VECTOR(1 downto 0));
-end component;
-
--- Configuration specification
- for all : wrapped_sfifo use entity XilinxCoreLib.sync_fifo_v4_0(behavioral)
- generic map(
- c_read_data_width => 8,
- c_has_wr_ack => 1,
- c_dcount_width => 2,
- c_has_wr_err => 1,
- c_wr_err_low => 0,
- c_wr_ack_low => 0,
- c_enable_rlocs => 0,
- c_has_dcount => 1,
- c_rd_err_low => 0,
- c_rd_ack_low => 0,
- c_read_depth => 16,
- c_has_rd_ack => 1,
- c_write_depth => 16,
- c_ports_differ => 0,
- c_memory_type => 0,
- c_write_data_width => 8,
- c_has_rd_err => 1);
-BEGIN
-
-U0 : wrapped_sfifo
- port map (
- clk => clk,
- sinit => sinit,
- din => din,
- wr_en => wr_en,
- rd_en => rd_en,
- dout => dout,
- full => full,
- empty => empty,
- rd_ack => rd_ack,
- wr_ack => wr_ack,
- rd_err => rd_err,
- wr_err => wr_err,
- data_count => data_count);
-END sfifo_a;
-
--- synopsys translate_on
-