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authorprot2004-03-14 23:44:05 +0000
committerprot2004-03-14 23:44:05 +0000
commit733998a6a054548033ce3c76924590eb773c1b22 (patch)
tree8859c49e6b58bb898cb1a68ffa0ab7e2ce454a91 /2004/n/fpga/src
parent7ce31c6698e8456f14740a830f93baed2272ad44 (diff)
Ajout de la première version qui marche du rxserie
Diffstat (limited to '2004/n/fpga/src')
-rw-r--r--2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd135
-rw-r--r--2004/n/fpga/src/portserie/rxserie/rxserie.npl38
-rw-r--r--2004/n/fpga/src/portserie/rxserie/rxserie.vhd253
-rw-r--r--2004/n/fpga/src/portserie/rxserie/sfifo.vhd119
-rw-r--r--2004/n/fpga/src/portserie/rxserie/sfifo.xco42
5 files changed, 587 insertions, 0 deletions
diff --git a/2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd b/2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd
new file mode 100644
index 0000000..ec71a5c
--- /dev/null
+++ b/2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd
@@ -0,0 +1,135 @@
+-- TestBench Template
+
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.ALL;
+ USE ieee.numeric_std.ALL;
+
+use work.nono_const.all;
+use work.isa_const.all;
+
+ ENTITY bch_rxserie IS
+ END bch_rxserie;
+
+ ARCHITECTURE behavior OF bch_rxserie IS
+
+-- Component Declaration
+ COMPONENT rxserie
+ PORT(
+ rst : in std_logic;
+ bus_clk : in std_logic;
+ rw : in std_logic; -- read (0) / write (1)
+ bus_data : inout T_DATA;
+ clk: in std_logic;
+ rxin: in std_logic;
+ irqFIFO: out std_logic;
+ irqRX: out std_logic;
+ csData : in std_logic;
+ csConfig : in std_logic;
+ csFlag : in std_logic);
+ END COMPONENT;
+
+
+
+signal rst: std_logic;
+signal bus_clk: std_logic;
+signal rw: std_logic;
+signal bus_data: T_DATA;
+signal data_received: T_DATA;
+signal clk: std_logic:='0';
+signal rxin: std_logic:='1';
+signal irqFIFO: std_logic;
+signal irqRX: std_logic;
+signal csData: std_logic;
+signal csConfig: std_logic;
+signal csFlag: std_logic;
+
+
+
+BEGIN
+
+ Inst_rxserie: rxserie PORT MAP(
+ rst => rst,
+ bus_clk => bus_clk,
+ rw => rw,
+ bus_data => bus_data,
+ clk => clk,
+ rxin => rxin,
+ irqFIFO => irqFIFO,
+ irqRX => irqRX,
+ csData => csData,
+ csConfig => csConfig,
+ csFlag => csFlag
+ );
+
+
+-- baudrate/(16*2) used to generate half clock cycle;
+clk <= (Not clk) after (CK_PERIOD/2);
+
+-- Reset Uart
+rst <= '1','0' after (10*CK_PERIOD);
+
+-- feeding back output from transmitter to the input of receiver
+rxin <= not rxin after 12 us;
+
+
+-- csData => csData,
+-- csConfig => csConfig,
+-- csFlag => csFlag
+
+
+check:process
+ -- procedure declaration
+ -- declared in process due to assignment to read
+ -- this procedure reads out data from the receiver
+ -- timing can be modified to model any CPU read cycle
+ PROCEDURE read_bus IS
+ BEGIN
+ rw <= '1';
+ bus_data<="ZZZZZZZZ";
+ WAIT FOR (ISA_CK_PERIOD/2);
+ bus_clk<='1';
+ WAIT FOR (ISA_CK_PERIOD/2);
+ data_received <= bus_data;
+ WAIT FOR 1 ns;
+ bus_clk<='0';
+ csFlag<='0';
+ csConfig<='0';
+ csData<='0';
+ WAIT FOR 25 ns;
+ END read_bus;
+
+ PROCEDURE write_bus(data : IN std_logic_vector(7 downto 0)) IS
+ --VARIABLE din : std_logic_vector(7 downto 0);
+ BEGIN
+ --din := conv_std_logic_vector(data,8);
+ rw <= '0';
+ bus_data <= data;
+ WAIT FOR (ISA_CK_PERIOD/2);
+ bus_clk <= '1';
+ WAIT FOR (ISA_CK_PERIOD/2);
+ bus_clk <= '0';
+ csFlag<='0';
+ csConfig<='0';
+ csData<='0';
+ bus_data <= (others => 'Z');
+ WAIT FOR 25 ns;
+ END write_bus;
+
+begin
+ csConfig<='1';
+ write_bus("00111111"); --(115200, toutes interruptions ok, On)
+
+ WAIT FOR 10 us;
+
+ csData<='1';
+ read_bus;
+
+ WAIT FOR 10 us;
+
+ csFlag<='1';
+ read_bus;
+
+ WAIT FOR 10 us;
+
+end process;
+END;
diff --git a/2004/n/fpga/src/portserie/rxserie/rxserie.npl b/2004/n/fpga/src/portserie/rxserie/rxserie.npl
new file mode 100644
index 0000000..597ac7c
--- /dev/null
+++ b/2004/n/fpga/src/portserie/rxserie/rxserie.npl
@@ -0,0 +1,38 @@
+JDF G
+// Created by Project Navigator ver 1.0
+PROJECT rxserie
+DESIGN rxserie
+DEVFAM spartan2
+DEVFAMTIME 0
+DEVICE xc2s200
+DEVICETIME 0
+DEVPKG pq208
+DEVPKGTIME 0
+DEVSPEED -6
+DEVSPEEDTIME 0
+DEVTOPLEVELMODULETYPE HDL
+TOPLEVELMODULETYPETIME 0
+DEVSYNTHESISTOOL XST (VHDL/Verilog)
+SYNTHESISTOOLTIME 0
+DEVSIMULATOR Modelsim
+SIMULATORTIME 0
+DEVGENERATEDSIMULATIONMODEL VHDL
+GENERATEDSIMULATIONMODELTIME 0
+SOURCE rxserie.vhd
+SOURCE ..\uart\rxcver.vhd
+STIMULUS ..\fifo\bch_sfifo.vhd
+SOURCE ..\fifo\fifodriver.vhd
+STIMULUS ..\fifo\bch_fifodriver.vhd
+SOURCE ..\clockgene\clockgene.vhd
+SOURCE ..\..\registre\registre.vhd
+SOURCE sfifo.xco
+STIMULUS bch_rxserie.vhd
+SOURCE ..\..\modele\nono_const.vhd
+SOURCE ..\..\modele\isa_const.vhd
+[Normal]
+p_CompxlibTargetSimulator=xstvhd, spartan2, Design.t_compLibraries, 1079088462, ModelSim SE
+[STATUS-ALL]
+rxserie.ngcFile=WARNINGS,1079226990
+rxserie.ngdFile=WARNINGS,1079300826
+[STRATEGY-LIST]
+Normal=True
diff --git a/2004/n/fpga/src/portserie/rxserie/rxserie.vhd b/2004/n/fpga/src/portserie/rxserie/rxserie.vhd
new file mode 100644
index 0000000..1ee58ec
--- /dev/null
+++ b/2004/n/fpga/src/portserie/rxserie/rxserie.vhd
@@ -0,0 +1,253 @@
+-- -------------------------------------------
+-- Port série RX pour le fpga robot
+-- -------------------------------------------
+--
+-- * Prend 3 adresses mémoire :
+-- 0 - Rxdata
+-- 1 - Flag : (x ! x ! FNE ! FFull ! FL3 ! FL2 ! FL1 ! FL0 )
+-- 2 - Config : (x ! x ! x ! On/Off ! FNEIF ! FFIF ! BdR1 ! BdR0)
+-- * Mettre le bit On/Off à 1 pour activer la reception
+-- * Chaque lecture dans rxdata dépile la donnée de la fifo
+-- * Dès que le registre à décalage est plein, il empile la donnée dans la
+-- fifo.
+-- * Deux bits de stop
+-- * Quand la fifo est pleine, met le flag FifoFull (FF) à 1. Chaque front
+-- montant du flag FF met à 1 le flag d'interruption FFIF et génère une
+-- interruption. Il faut alors mettre à 0 FFIF, qui sera remis à 1 au
+-- prochain front montant de FF
+-- * Quand il y a au moins une donnée dans la pile, le bit FifiNonEmpty (FNE)
+-- est à 1. Quand FNE passe de 0 à 1, le flag FNEIF passe à 1 et génère une
+-- interruption. Il faut alors mettre à 0 FNEIF, qui repassera à 1 au
+-- prochain front montant de FNE
+-- * On peut lire l'état de la pile dans le registre de flags (FifoLevel1/0)
+-- * Baudrate disponible :
+-- BdR1/0 ! Baudrate
+-- 00 ! 9600
+-- 01 ! 19200
+-- 10 ! 57600
+-- 11 ! 115200
+
+
+-- Config : (x ! x ! EIEn ! On/Off ! DRIEn ! FFIEn ! BdR1 ! BdR0)
+-- Flag : (x ! PErr ! FErr ! OErr ! Empty ! Full ! FLI1 ! FLI0 )
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+use work.nono_const.all;
+
+entity rxserie is
+ port (
+ rst : in std_logic;
+ bus_clk : in std_logic;
+ rw : in std_logic; -- read (0) / write (1)
+ bus_data : inout T_DATA;
+ clk: in std_logic;
+ rxin: in std_logic;
+ irqFIFO: out std_logic;
+ irqRX: out std_logic;
+ irqERR: out std_logic;
+ csData : in std_logic;
+ csConfig : in std_logic;
+ csFlag : in std_logic
+ );
+end rxserie;
+
+architecture rtl of rxserie is
+-- composants
+component clockgene
+ port(
+ rst: in std_logic;
+ ckin: in std_logic;
+ ckout: out std_logic;
+ param: in std_logic_vector(1 downto 0)
+ );
+end component;
+
+component regIO
+ port(
+ cs: in std_logic;
+ bus_data: inout T_DATA;
+ input: in T_DATA;
+ output: out T_DATA;
+ rw: in std_logic;
+ load: in std_logic;
+ ck: in std_logic;
+ rst: in std_logic);
+end component;
+
+component fifodriver
+ port(
+ clk: in std_logic;
+ rst: in std_logic;
+ readreq: in std_logic;
+ writereq: in std_logic;
+ din: IN std_logic_VECTOR(7 downto 0);
+ dout: OUT std_logic_VECTOR(7 downto 0);
+ dready: out std_logic;
+ full: OUT std_logic;
+ empty: OUT std_logic;
+ data_count: OUT std_logic_VECTOR(1 downto 0));
+END COMPONENT;
+
+component RXCVER
+ port (
+ MCLKX16 : in std_logic; -- input clock, 16x baudrate clock used for synchronization
+ READ : in std_logic; -- Read Strobe
+ RX : in std_logic; -- Receive Input Line
+ RESET : in std_logic; -- Global Reset
+ RXRDY : out std_logic; -- Receiver data ready to read
+ PARITY_ERR : out std_logic; -- Receiver parity error flag
+ FRAMING_ERR : out std_logic; -- Receiver framing error flag
+ OVERRUN : out std_logic; -- Receiver overrun error flag
+ DATA : out std_logic_vector(7 downto 0) -- 8 bit output data bus
+ );
+end component;
+
+
+-- signaux
+signal rxready:std_logic; -- Receiver data ready to read
+signal rxread:std_logic;
+signal rxparERR:std_logic:='0'; -- Receiver parity error flag
+signal rxfrmERR:std_logic:='0'; -- Receiver framing error flag
+signal rxovrrERR:std_logic:='0'; -- Receiver overrun error flag
+
+signal rxck: std_logic;
+signal geneck:std_logic;
+
+signal fifoEmpty: std_logic;
+signal fifoFull: std_logic;
+signal fifoLevel: std_logic_vector(1 downto 0);
+signal fifopurge: std_logic:='0';
+signal fifockin: std_logic;
+signal fifockout: std_logic;
+signal fifodready: std_logic;
+
+signal confreg: T_DATA:="00000000";
+signal flagreg: T_DATA:="00000000";
+signal inter_data: T_DATA;
+signal inter_bus: T_DATA;
+signal inter_fifo: T_DATA;
+
+signal state_rx_read:integer:=0;
+
+signal dummy : T_DATA :=(others =>'0');
+signal un: std_logic :='1';
+
+
+begin
+CLOCK1 : clockgene
+port map(
+ rst => rst,
+ ckin=>geneck,
+ ckout=>rxck,
+ param=>confreg(1 downto 0));
+
+FIFO1: fifodriver port map(
+ clk => clk,
+ rst => fifopurge,
+ readreq => fifockout,
+ writereq => fifockin,
+ din => inter_data,
+ dout => inter_fifo,
+ dready => fifodready,
+ full => fifoFull,
+ empty => fifoEmpty,
+ data_count => fifoLevel(1 downto 0));
+
+-- Config : (x ! x ! EIEn ! On/Off ! DRIEn ! FFIEn ! BdR1 ! BdR0)
+RCONF : regIO port map(
+ cs=>csConfig,
+ bus_data=>bus_data,
+ input=>dummy,
+ output=>confreg,
+ rw=>rw,
+ load=>dummy(0),
+ ck=>bus_clk,
+ rst=>rst);
+
+-- Flag : (x ! PErr ! FErr ! OErr ! Empty ! Full ! FLI1 ! FLI0 )
+RFLAG : regIO port map(
+ cs=>csFlag,
+ bus_data=>bus_data,
+ input=>flagreg,
+ output=>open,
+ rw=>rw,
+ load=>un,
+ ck=>bus_clk,
+ rst=>rst);
+
+RC1:RXCVER
+port map(
+ MCLKX16 =>rxck, -- input clock, 16x baudrate clock used for synchronization
+ READ =>rxread, --rxread, -- Read Strobe
+ RX =>rxin, -- Receive Input Line
+ RESET =>rst, -- Global Reset
+ RXRDY =>rxready, -- Receiver data ready to read
+ PARITY_ERR =>rxparERR, -- Receiver parity error flag
+ FRAMING_ERR =>rxfrmERR, -- Receiver framing error flag
+ OVERRUN =>rxovrrERR, -- Receiver overrun error flag
+ DATA =>inter_data -- 8 bit output data bus
+ );
+
+
+-- config
+geneck <= (confreg(4) and clk); -- On/Off et masterck --confreg(4)
+fifopurge<=rst;
+
+-- flags
+flagreg(1 downto 0) <= fifoLevel(1 downto 0);
+flagreg(2) <= fifoFull;
+flagreg(3) <= fifoEmpty;
+flagreg(4) <= rxparERR; -- Receiver parity error flag
+flagreg(5) <= rxfrmERR; -- Receiver framing error flag
+flagreg(6) <= rxovrrERR; -- Receiver overrun error flag
+
+
+-- controle des flux
+fifockout <= (csData and bus_clk and rw and (not rst));
+fifockin <= ((not rxread) and (not fifoFull));
+
+inter_bus <= inter_fifo when (fifockout='1') else (others => 'Z');
+
+bus_data <= inter_bus;
+
+-- irq
+irqFifo <= (fifoLevel(1) and fifoLevel(0)) and confreg(2); --fifo almost full AND Int/En
+irqRx <= (not fifoEmpty) and confreg(3);
+irqErr <= (rxparERR or rxovrrERR or rxfrmERR or fifoFull) and confreg(5);
+
+-- sortie de donnée du récepteur
+process(rxck)
+begin
+ if(rxck'event and rxck='1') then
+ rxread<='1';
+ case state_rx_read is
+ when 0 => if(rxready='1') then
+ state_rx_read<=1;
+ end if;
+ when 1 => state_rx_read<=2;
+ when 2 => rxread<='0';
+ state_rx_read<=3;
+ when 3 => if(rxready='0') then
+ state_rx_read<=0;
+ end if;
+ when others => null;
+ end case;
+ end if;
+end process;
+
+end rtl;
+
+
+
+
+
+
+
+
+
+
diff --git a/2004/n/fpga/src/portserie/rxserie/sfifo.vhd b/2004/n/fpga/src/portserie/rxserie/sfifo.vhd
new file mode 100644
index 0000000..7455e8a
--- /dev/null
+++ b/2004/n/fpga/src/portserie/rxserie/sfifo.vhd
@@ -0,0 +1,119 @@
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used --
+-- solely for design, simulation, implementation and creation of --
+-- design files limited to Xilinx devices or technologies. Use --
+-- with non-Xilinx devices or technologies is expressly prohibited --
+-- and immediately terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
+-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
+-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
+-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
+-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
+-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
+-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
+-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
+-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
+-- FOR A PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support --
+-- appliances, devices, or systems. Use in such applications are --
+-- expressly prohibited. --
+-- --
+-- (c) Copyright 1995-2003 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file sfifo.vhd when simulating
+-- the core, sfifo. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Guide".
+
+-- The synopsys directives "translate_off/translate_on" specified
+-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+-- synopsys translate_off
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+Library XilinxCoreLib;
+ENTITY sfifo IS
+ port (
+ clk: IN std_logic;
+ sinit: IN std_logic;
+ din: IN std_logic_VECTOR(7 downto 0);
+ wr_en: IN std_logic;
+ rd_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(7 downto 0);
+ full: OUT std_logic;
+ empty: OUT std_logic;
+ rd_ack: OUT std_logic;
+ wr_ack: OUT std_logic;
+ rd_err: OUT std_logic;
+ wr_err: OUT std_logic;
+ data_count: OUT std_logic_VECTOR(1 downto 0));
+END sfifo;
+
+ARCHITECTURE sfifo_a OF sfifo IS
+
+component wrapped_sfifo
+ port (
+ clk: IN std_logic;
+ sinit: IN std_logic;
+ din: IN std_logic_VECTOR(7 downto 0);
+ wr_en: IN std_logic;
+ rd_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(7 downto 0);
+ full: OUT std_logic;
+ empty: OUT std_logic;
+ rd_ack: OUT std_logic;
+ wr_ack: OUT std_logic;
+ rd_err: OUT std_logic;
+ wr_err: OUT std_logic;
+ data_count: OUT std_logic_VECTOR(1 downto 0));
+end component;
+
+-- Configuration specification
+ for all : wrapped_sfifo use entity XilinxCoreLib.sync_fifo_v4_0(behavioral)
+ generic map(
+ c_read_data_width => 8,
+ c_has_wr_ack => 1,
+ c_dcount_width => 2,
+ c_has_wr_err => 1,
+ c_wr_err_low => 0,
+ c_wr_ack_low => 0,
+ c_enable_rlocs => 0,
+ c_has_dcount => 1,
+ c_rd_err_low => 0,
+ c_rd_ack_low => 0,
+ c_read_depth => 16,
+ c_has_rd_ack => 1,
+ c_write_depth => 16,
+ c_ports_differ => 0,
+ c_memory_type => 0,
+ c_write_data_width => 8,
+ c_has_rd_err => 1);
+BEGIN
+
+U0 : wrapped_sfifo
+ port map (
+ clk => clk,
+ sinit => sinit,
+ din => din,
+ wr_en => wr_en,
+ rd_en => rd_en,
+ dout => dout,
+ full => full,
+ empty => empty,
+ rd_ack => rd_ack,
+ wr_ack => wr_ack,
+ rd_err => rd_err,
+ wr_err => wr_err,
+ data_count => data_count);
+END sfifo_a;
+
+-- synopsys translate_on
+
diff --git a/2004/n/fpga/src/portserie/rxserie/sfifo.xco b/2004/n/fpga/src/portserie/rxserie/sfifo.xco
new file mode 100644
index 0000000..afcd6a7
--- /dev/null
+++ b/2004/n/fpga/src/portserie/rxserie/sfifo.xco
@@ -0,0 +1,42 @@
+# Xilinx CORE Generator 6.1.03i
+# Username = Administrateur
+# COREGenPath = D:\xilinx\coregen
+# ProjectPath = D:\vhdl\robot\carte_fpga\src\portserie\rxserie
+# ExpandedProjectPath = D:\vhdl\robot\carte_fpga\src\portserie\rxserie
+# OverwriteFiles = true
+# Core name: sfifo
+# Number of Primitives in design: 87
+# Number of CLBs used in design cannot be determined when there is no RPMed logic
+# Number of Slices used in design cannot be determined when there is no RPMed logic
+# Number of LUT sites used in design: 43
+# Number of LUTs used in design: 35
+# Number of REG used in design: 22
+# Number of SRL16s used in design: 8
+# Number of Distributed RAM primitives used in design: 0
+# Number of Block Memories used in design: 0
+# Number of Dedicated Multipliers used in design: 0
+# Number of HU_SETs used: 0
+#
+SET BusFormat = BusFormatAngleBracketNotRipped
+SET XilinxFamily = Spartan2
+SET OutputOption = OutputProducts
+SET FlowVendor = Foundation_iSE
+SET FormalVerification = None
+SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim
+SELECT Synchronous_FIFO Spartan2 Xilinx,_Inc. 4.0
+CSET data_width = 8
+CSET read_error_sense = active_high
+CSET read_error_flag = true
+CSET write_acknowledge_flag = true
+CSET write_error_flag = true
+CSET data_count = true
+CSET memory_type = Distributed_Memory
+CSET read_acknowledge_sense = active_high
+CSET component_name = sfifo
+CSET fifo_depth = 16
+CSET read_acknowledge_flag = true
+CSET data_count_width = 2
+CSET write_error_sense = active_high
+CSET write_acknowledge_sense = active_high
+GENERATE
+