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authorgalmes2004-02-28 21:20:24 +0000
committergalmes2004-02-28 21:20:24 +0000
commite1e70c340f3a67a98e39fa8fa7d76b8e50f7448e (patch)
treecc9765a7c48590785e4850af8cc28c1e40d990b8 /2004/n/fpga/src
parent10dfed049dd27dd03712c9fe1042e0620c318c32 (diff)
Suppression des fichiers tristate de gpio
Diffstat (limited to '2004/n/fpga/src')
-rw-r--r--2004/n/fpga/src/gpio/bch_tristate.vhd56
-rw-r--r--2004/n/fpga/src/gpio/tristate.vhd31
2 files changed, 0 insertions, 87 deletions
diff --git a/2004/n/fpga/src/gpio/bch_tristate.vhd b/2004/n/fpga/src/gpio/bch_tristate.vhd
deleted file mode 100644
index a31c03e..0000000
--- a/2004/n/fpga/src/gpio/bch_tristate.vhd
+++ /dev/null
@@ -1,56 +0,0 @@
--- bch_tristate.vhd
--- Eurobot 2004 : APB Team
--- Auteur : Pierre-André Galmes
--- Test de tristate.
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-use work.isa_const.all;
-use work.nono_const.all;
-
-
-entity bch_tristate is
-end bch_tristate;
-
-architecture sim1 of bch_tristate is
-
- component tristate
- port (
- enable : in std_logic;
- data_in : in T_DATA;
- data_out : out T_DATA
- );
- end component;
-
- -- définiton des signaux
- signal enable : std_logic;
- signal data_in : T_DATA;
- signal data_out : T_DATA;
-
-begin
- U1 : tristate port map (
- enable => enable,
- data_in => data_in,
- data_out => data_out
- );
-
- enable <= '0',
- '1' after 2*CK_PERIOD,
- '0' after 3*CK_PERIOD,
- '1' after 5*CK_PERIOD,
- '0' after 6*CK_PERIOD;
- data_in <= x"01",
- x"02" after 3*CK_PERIOD,
- x"06" after 5*CK_PERIOD;
- --x"03" after 5*CK_PERIOD;
-end sim1;
-
-configuration cf1_bch_tristate of bch_tristate is
- for sim1
- for all : tristate use entity work.tristate(RTL); end for;
- end for;
-end cf1_bch_tristate;
-
diff --git a/2004/n/fpga/src/gpio/tristate.vhd b/2004/n/fpga/src/gpio/tristate.vhd
deleted file mode 100644
index 07e440e..0000000
--- a/2004/n/fpga/src/gpio/tristate.vhd
+++ /dev/null
@@ -1,31 +0,0 @@
--- tristate.vhd
--- Eurobot 2004 : APB Team
--- Auteur : Pierre-André Galmes
--- Registre dont la valeur est accessible en lecture.
-
--- Principe :
--- Bloc trois états (three-state) qui met les sorties en hautes impédance si
--- elle ne sont pas "enabled".
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-use work.isa_const.all;
-use work.nono_const.all;
-
-
-entity tristate is
- port (
- enable : in std_logic;
- data_in : in T_DATA;
- data_out : out T_DATA
- );
-end entity;
-
-architecture RTL of tristate is
-begin
- -- partie combinatoire.
- data_out <= data_in when (enable = '1') else (others => 'Z');
-end RTL;