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authorgalmes2004-02-28 21:28:07 +0000
committergalmes2004-02-28 21:28:07 +0000
commit6926a945f5ffe7c996676e9557fee7e22e03a696 (patch)
treea41d542aa2239f3b48eea1d5dd34291b95636dd6 /2004/n/fpga/src
parente1e70c340f3a67a98e39fa8fa7d76b8e50f7448e (diff)
Ajout de fichiers.
Diffstat (limited to '2004/n/fpga/src')
-rw-r--r--2004/n/fpga/src/interrupt/bch_reg_8.vhd54
-rw-r--r--2004/n/fpga/src/interrupt/reg_8.vhd33
2 files changed, 87 insertions, 0 deletions
diff --git a/2004/n/fpga/src/interrupt/bch_reg_8.vhd b/2004/n/fpga/src/interrupt/bch_reg_8.vhd
new file mode 100644
index 0000000..4538de2
--- /dev/null
+++ b/2004/n/fpga/src/interrupt/bch_reg_8.vhd
@@ -0,0 +1,54 @@
+-- bch_reg_8.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre-André Galmes
+-- test bench du registre 8 bits
+
+library ieee;
+use ieee.std_logic_1164.all;
+--use ieee.std_logic_arith.all;
+
+use work.nono_const.all;
+
+entity bch_reg_8 is
+end bch_reg_8;
+
+architecture sim_1 of bch_reg_8 is
+ component reg_8
+ port(
+ rst : in std_logic;
+ clk : in std_logic;
+ en : in std_logic; -- enable
+ input : in std_logic_vector (7 downto 0);
+ output : out std_logic_vector (7 downto 0)
+ );
+ end component;
+ signal rst : std_logic;
+ signal clk : std_logic := '0';
+ signal en : std_logic := '0';
+ signal input : std_logic_vector (7 downto 0);
+ signal output : std_logic_vector (7 downto 0);
+
+ begin
+ U0 : reg_8 port map (rst => rst, clk => clk, en => en,
+ input => input, output => output);
+
+ rst <= '1', '0' after (CK_PERIOD/5);
+ clk <= not clk after CK_PERIOD/2;
+ en <= '0',
+ '1' after (CK_PERIOD*1),
+ '0' after (CK_PERIOD*3),
+ '1' after (CK_PERIOD*5),
+ '0' after (CK_PERIOD*7);
+ input <= x"00",
+ x"05" after (CK_PERIOD/2),
+ x"01" after (CK_PERIOD*3);
+
+end sim_1;
+
+--configuration
+
+configuration cf_bch_reg_8 of bch_reg_8 is
+ for sim_1
+ for U0 : reg_8 use entity work.reg_8(RTL); end for;
+ end for;
+end cf_bch_reg_8;
diff --git a/2004/n/fpga/src/interrupt/reg_8.vhd b/2004/n/fpga/src/interrupt/reg_8.vhd
new file mode 100644
index 0000000..f32f7d9
--- /dev/null
+++ b/2004/n/fpga/src/interrupt/reg_8.vhd
@@ -0,0 +1,33 @@
+-- reg_8.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre-André Galmes
+-- Registre 8 bits.
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+
+entity reg_8 is
+ port (
+ rst : in std_logic;
+ clk : in std_logic;
+ en : in std_logic; -- enable
+ input : in std_logic_vector (7 downto 0);
+ output : out std_logic_vector (7 downto 0)
+ );
+end reg_8;
+
+architecture RTL of reg_8 is
+begin
+ process (rst, clk)
+ begin
+ if (rst ='1') then
+ output <= x"00";
+ elsif (clk'event and clk = '1') then
+ if (en='1') then
+ output <= input;
+ end if;
+ end if;
+ end process;
+end RTL;