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authorprot2004-03-15 00:04:52 +0000
committerprot2004-03-15 00:04:52 +0000
commit3081317e0e8ab5906766e7281cc838378c926bab (patch)
tree6317e4268ed8ac7335394eb2a27171008d9eb40f /2004/n/fpga/src
parent2698ec1d2251323bdcc992295179c76b4686ab1e (diff)
menage anciens
Diffstat (limited to '2004/n/fpga/src')
-rw-r--r--2004/n/fpga/src/portserie/bch_txserie.vhd140
-rw-r--r--2004/n/fpga/src/portserie/clockgene.vhd27
-rw-r--r--2004/n/fpga/src/portserie/decoder.vhd35
-rw-r--r--2004/n/fpga/src/portserie/fifodriver.vhd91
-rw-r--r--2004/n/fpga/src/portserie/modele.vhd15
-rw-r--r--2004/n/fpga/src/portserie/portserie.sws192
-rw-r--r--2004/n/fpga/src/portserie/rxserie.vhd29
-rw-r--r--2004/n/fpga/src/portserie/txserie.vhd210
8 files changed, 0 insertions, 739 deletions
diff --git a/2004/n/fpga/src/portserie/bch_txserie.vhd b/2004/n/fpga/src/portserie/bch_txserie.vhd
deleted file mode 100644
index d1aa1e3..0000000
--- a/2004/n/fpga/src/portserie/bch_txserie.vhd
+++ /dev/null
@@ -1,140 +0,0 @@
--- modele.vhd
--- Eurobot 2004 : APB Team
--- Auteur : Pierre-André Galmes
--- Fichier modèle pour la déclaration de module.
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-use work.nono_const.all;
-
-
-entity bch_txserie is
-end bch_txserie;
-
-architecture sim1 of bch_txserie is
-
- component txserie
- generic (
- -- adresses des différents registres du module.
- A_DATA : T_ADDRESS ;
- A_CONFIG : T_ADDRESS ;
- A_FLAG : T_ADDRESS
- -- si autre choses à déclarer...
- );
- port (
- rst : in std_logic;
- clk : in std_logic;
- rw : in std_logic; -- read (0) / write (1)
- bus_data : inout T_DATA;
- bus_address : in T_ADDRESS;
- masterck: in std_logic;
- txout: out std_logic;
- minIRQ: out std_logic
- );
- end component;
-
-
--- définiton des signaux
-signal rst : std_logic;
-signal clk : std_logic := '0';
-signal simclk : std_logic := '0';
-signal rw : std_logic; -- read / write
-signal bus_data : T_DATA:="00000000";
-signal bus_address : T_ADDRESS;
-signal masterck: std_logic:='0';
-signal txout: std_logic;
-signal minIRQ: std_logic;
-signal state_next:integer:=0;
-
-begin
- U1 : txserie
- generic map (
- -- Définition des addresses.
- A_DATA => "0000000001",
- A_CONFIG => "0000000010",
- A_FLAG => "0000000011"
- )
- port map (
- rst => rst,
- clk => clk,
- rw => rw,
- bus_data => bus_data,
- bus_address => bus_address,
- masterck=> masterck,
- txout=> txout,
- minIRQ=> minIRQ
- );
-
-
- masterck<= not masterck after (CK_PERIOD/11);
- simclk<= not simclk after (CK_PERIOD/2);
-
-
- process(simclk)
- begin
- if(simclk'event and simclk='1') then
- state_next<=(state_next + 1);
- end if;
- end process;
-
- process(state_next)
- begin
- bus_address<="0000000000";
- clk<='0';
- rst<='0';
- bus_data<=(others =>'Z');
-
- case state_next is
- when 1 => bus_address<="0000000010";
- bus_data<="00010111";
- rw<='0';
- when 2 => bus_address<="0000000010";
- bus_data<="00010111";
- rw<='0';
- clk<='1';
- when 3 => null;
-
- when 4 => bus_address<="0000000001";
- bus_data<="00010111";
- rw<='0';
- when 5 => bus_address<="0000000001";
- bus_data<="00010111";
- rw<='0';
- clk<='1';
- when 6 => null;
-
- when 7 => bus_address<="0000000011";
- rw<='1';
- when 8 => bus_address<="0000000011";
- rw<='1';
- clk<='1';
- when 9 => null;
-
-
- when 10 => bus_address<="0000000010";
- rw<='1';
- when 11 => bus_address<="0000000010";
- rw<='1';
- clk<='1';
- when 12 => null;
-
- when others => null;
- end case;
- end process;
-end sim1;
-
-
-configuration cf1_bch_txserie of bch_txserie is
- for sim1
- for all : txserie use entity work.txserie(rtl); end for;
- end for;
-end cf1_bch_txserie;
-
-
-
-
-
-
diff --git a/2004/n/fpga/src/portserie/clockgene.vhd b/2004/n/fpga/src/portserie/clockgene.vhd
deleted file mode 100644
index 2a13a8c..0000000
--- a/2004/n/fpga/src/portserie/clockgene.vhd
+++ /dev/null
@@ -1,27 +0,0 @@
--- clockgene.vhd
--- Eurobot 2004 : APB Team
--- Auteur : Pierre Prot
--- clock
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-use work.nono_const.all;
-
--- horloge de ref
-entity clockgene is
- port(
- ckin: in std_logic;
- ckout: out std_logic;
- param: in std_logic_vector(1 downto 0)
- );
-end clockgene;
-
-architecture rtl of clockgene is
-begin
- ckout<=ckin;
-end rtl;
-
-
diff --git a/2004/n/fpga/src/portserie/decoder.vhd b/2004/n/fpga/src/portserie/decoder.vhd
deleted file mode 100644
index 4eb4724..0000000
--- a/2004/n/fpga/src/portserie/decoder.vhd
+++ /dev/null
@@ -1,35 +0,0 @@
--- decoder.vhd
--- Eurobot 2004 : APB Team
--- Auteur : Pierre Prot
--- décodeur
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-use work.nono_const.all;
-
-entity decoder is
- generic(adr : T_ADDRESS:="0000000000");
- port(
- bus_address : in T_ADDRESS;
- cs: out std_logic:='0'
- );
-end decoder;
-
-architecture rtl of decoder is
-begin
-process(bus_address)
-begin
- if(bus_address = adr)
- then
- cs<='1';
- else
- cs<='0';
- end if;
-end process;
-end rtl;
-
-
-
diff --git a/2004/n/fpga/src/portserie/fifodriver.vhd b/2004/n/fpga/src/portserie/fifodriver.vhd
deleted file mode 100644
index f3f1d1b..0000000
--- a/2004/n/fpga/src/portserie/fifodriver.vhd
+++ /dev/null
@@ -1,91 +0,0 @@
--- fifodriver.vhd
--- Eurobot 2004 : APB Team
--- Auteur : Pierre Prot
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-use work.nono_const.all;
-
--- pilote de fifo
-entity fifodriver is
- port(
- masterck,reset: in std_logic;
- readreq,writereq: in std_logic;
- fifock:out std_logic;
- fiforead:out std_logic;
- fifowrite:out std_logic
- );
- constant PRESCAL :integer:= 1;
-end fifodriver;
-
--- arch
-architecture rtl of fifodriver is
-signal clock:std_logic;
-signal writeflag,readflag :std_logic;
-signal subck : integer :=0;
-
-begin
- fifock<=clock;
-
--- process(writereq)
--- begin
--- if (writereq'event and writereq='1') then
--- writeflag<='1';
--- end if;
--- end process;
-
--- process(readreq)
--- begin
--- if (readreq'event and readreq='1') then
--- readflag<='1';
--- end if;
--- end process;
-
- process(clock,writereq,readreq)
- begin
- if (writereq'event and writereq='1') then
- writeflag<='1';
- end if;
-
- if (readreq'event and readreq='1') then
- readflag<='1';
- end if;
-
- -- sur front descendant de fifock, on met fifowrite et fiforead à
- -- jour
- if(clock'event and clock='0') then
- if(readflag='1') then
- readflag<='0';
- fiforead<='1';
- end if;
-
- if(writeflag='1') then
- writeflag<='0';
- fifowrite<='1';
- end if;
- end if;
- end process;
-
--- la partie SEQU : divise la fréquence d'horloge
- SEQU:process(masterck)
- begin
- if (masterck'event and masterck='1') then
- if(subck=PRESCAL) then
- subck<=0;
- clock<='1';
- else
- subck<=subck+1;
- clock<='0';
- end if;
- end if;
- end process SEQU;
-end rtl;
-
-
-
-
-
-
diff --git a/2004/n/fpga/src/portserie/modele.vhd b/2004/n/fpga/src/portserie/modele.vhd
deleted file mode 100644
index a9f700b..0000000
--- a/2004/n/fpga/src/portserie/modele.vhd
+++ /dev/null
@@ -1,15 +0,0 @@
-entity modele is
- generic (
- -- adresses des différents registres du module.
- A_REG1 : T_ADDRESS;
- A_REG2 : T_ADDRESS;
- A_REG3 : T_ADDRESS
- -- si autre choses à déclarer...
- );
- port (
- rst : in std_logic;
- clk : in std_logic;
- rw : in std_logic; -- read (0) / write (1)
- bus_data : inout T_DATA;
- bus_address : in T_ADDRESS
-
diff --git a/2004/n/fpga/src/portserie/portserie.sws b/2004/n/fpga/src/portserie/portserie.sws
deleted file mode 100644
index e7939dc..0000000
--- a/2004/n/fpga/src/portserie/portserie.sws
+++ /dev/null
@@ -1,192 +0,0 @@
-#
-# This file has been automatically generated by the Symphony EDA IDE
-# Please do NOT modify this file manually. If you do, do it with
-# extreme care. This file represents your project settings. Corrupting
-# this file can render this file useless!!!
-#
-# Begin version identification section
-[version]
- version = 1
-[]
-# Begin libraries section (used by all tools)
-[libraries]
- ieee = $SYMPHONYEDA/lib/ieee/ieee.sym
- portserie = portserie.sym
-[]
-# End of libraries section
- [options]
- [booloption]
- name = -strict
- value = 0
- invert = 0
- []
- [booloption]
- name = -s
- value = 0
- invert = 0
- []
- [stringoption]
- name = -breakon
- value = FAILURE
- []
- [stringoption]
- name = -stdin
- value = ""
- []
- [stringoption]
- name = -stdout
- value = ""
- []
- [stringoption]
- name = -coverage
- value = ""
- []
- [multistringoption]
- name = -nowarn
- []
- [multistringoption]
- name = -noaccel
- []
- [multistringoption]
- name = -sdftyp
- []
- [multistringoption]
- name = -sdfmin
- []
- [multistringoption]
- name = -sdfmax
- []
- []
-# Begin description of library ieee
-[library]
- name = ieee
- [options]
- [booloption]
- name = -87
- value = 0
- invert = 0
- []
- [booloption]
- name = -x
- value = 0
- invert = 0
- []
- [booloption]
- name = -s
- value = 1
- invert = 0
- []
- [booloption]
- name = -strict
- value = 0
- invert = 0
- []
- [intoption]
- name = -maxerrors
- value = 10
- []
- [booloption]
- name = -autoorder
- value = 1
- invert = 0
- []
- []
-[]
-# End description of library ieee
-# Begin description of library portserie
-[library]
- name = portserie
- toplevel = bch_txserie
- [options]
- [booloption]
- name = -87
- value = 0
- invert = 0
- []
- [booloption]
- name = -x
- value = 0
- invert = 0
- []
- [booloption]
- name = -s
- value = 1
- invert = 0
- []
- [booloption]
- name = -strict
- value = 0
- invert = 0
- []
- [intoption]
- name = -maxerrors
- value = 10
- []
- [booloption]
- name = -autoorder
- value = 1
- invert = 0
- []
- []
- [file]
- name = ../modele/isa_const.vhd
- [options]
- []
- []
- [file]
- name = ../modele/nono_const.vhd
- [options]
- []
- []
- [file]
- name = ../registre/registre.vhd
- [options]
- []
- []
- [file]
- name = fifodriver.vhd
- [options]
- []
- []
- [file]
- name = fifo.vhd
- [options]
- []
- []
- [file]
- name = decoder.vhd
- [options]
- []
- []
- [file]
- name = clockgene.vhd
- [options]
- []
- []
- [file]
- name = txserie.vhd
- [options]
- []
- []
- [file]
- name = bch_txserie.vhd
- [options]
- []
- []
- [file]
- name = fifo/fifobehav.vhd
- [options]
- []
- []
- [file]
- name = txmit.vhd
- [options]
- []
- []
-[]
-# End description of library portserie
-# Begin various workspace properties
-[properties]
- work =portserie
-[]
-# End workspace properties
diff --git a/2004/n/fpga/src/portserie/rxserie.vhd b/2004/n/fpga/src/portserie/rxserie.vhd
deleted file mode 100644
index d53f129..0000000
--- a/2004/n/fpga/src/portserie/rxserie.vhd
+++ /dev/null
@@ -1,29 +0,0 @@
--- -------------------------------------------
--- Adaptateur de bus isa pour le fpga robot
--- -------------------------------------------
-
-library ieee;
-library ieee.std_logic_1164.all;
-
-
-entity adaptisa is
- port (
- bus_address_in : in T_ADDRESS_ISA;
- cs: std_logic_vector(NB_ADDRESS_REG-1 downto 0);
- csbank: std_logic_vector(NB_ADDRESS_BANK-1 downto 0);
- );
-end adaptisa;
-
-architecture rtl of adaptisa is
-
-begin
-
-process()
-begin
-
-end process;
-
-end rtl;
-
-
-
diff --git a/2004/n/fpga/src/portserie/txserie.vhd b/2004/n/fpga/src/portserie/txserie.vhd
deleted file mode 100644
index ee76e52..0000000
--- a/2004/n/fpga/src/portserie/txserie.vhd
+++ /dev/null
@@ -1,210 +0,0 @@
--- txserie.vhd
--- Eurobot 2004 : APB Team
--- Auteur : Pierre Prot
-
--- -------------------------------------------
--- Port série TX pour le fpga robot
--- -------------------------------------------
---
--- * Prend 3 adresses mémoire :
--- 0 - Txdata
--- 1 - Flag : (x ! x ! x ! x ! Empty ! Full/Int ! FLI1 ! FLI0)
--- 2 - Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0)
--- * Mettre le bit On/Off à 1 pour activer la transmission
--- * Chaque écriture dans txdata charge la donnée dans la fifo
--- * Dès que le registre à décalage est vide, il enlève le dernier élément de
--- la fifo et le transmet
--- * Deux bits de stop
--- * Quand la fifo est pleine, met le flag Full/Int à 1 et génère une
--- interruption. Il faut alors mettre à 0 le bit IntEn, qui sera remis à 1 à
--- la prochaine écriture dans la fifo
--- * On peut lire l'état de la pile dans le registre de flags
--- * On peut vider la pile en mettant Purge à 1
--- * Baudrate disponible :
--- BdR1/0 ! Baudrate
--- 00 ! 9600
--- 01 ! 19200
--- 10 ! 57600
--- 11 ! 115200
-
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-use work.nono_const.all;
-
-entity txserie is
- port (
- rst : in std_logic;
- clk : in std_logic;
- rw : in std_logic; -- read (0) / write (1)
- bus_data : inout T_DATA;
- masterck: in std_logic;
- txout: out std_logic;
- minIRQ: out std_logic
-
- csData : in std_logic;
- csConfig : in std_logic;
- csFlag : in std_logic;
- );
-end txserie;
-
-architecture rtl of txserie is
-
-component regIO
- port(
- cs: in std_logic;
- bus_data: inout T_DATA;
- input: in T_DATA;
- output: out T_DATA;
- rw: in std_logic;
- load: in std_logic;
- ck: in std_logic;
- rst: in std_logic
- );
-end component;
-
-
-component fifo is
- port(
- data_in: in T_DATA;
- data_out: out T_DATA;
- ck: in std_logic;
- ck_in: in std_logic;
- ck_out: in std_logic;
- flags: out std_logic_vector(5 downto 0);
- purge: in std_logic
- );
-end component;
-
-
-entity TXMIT is
- port (
- MCLKX16 : in std_logic;
- WRITE : in std_logic;
- RESET : in std_logic;
- DATA : in std_logic_vector(7 downto 0);
-
- TX : out std_logic;
- TXRDY : out std_logic
- );
-end TXMIT;
-
-component clockgene
- port(
- ckin: in std_logic;
- ckout: out std_logic;
- param: in std_logic_vector(1 downto 0)
- );
-end component;
-
-component decoder
- generic(adr : T_ADDRESS);
- port(
- bus_address: in T_DATA;
- cs: out std_logic
- );
-end component;
-
-
-signal fifoEmpty: std_logic;
-signal fifoFull: std_logic;
-signal fifoLI1: std_logic;
-signal fifoLI0: std_logic;
---signal BdR1: std_logic;
---signal BdR0: std_logic;
-signal fifopurge: std_logic:='0';
-signal fifoflags: std_logic_vector(5 downto 0);
-signal fifockin: std_logic;
-signal fifockout: std_logic;
-
-signal txck: std_logic;
-signal confreg: T_DATA;
-signal flagreg: T_DATA:="00000000";
-signal inter_data: T_DATA;
-signal txready: std_logic:='1';
-
-begin
-FIFO1: fifo
- port map(
- data_in=>bus_data,
- data_out=>inter_data,
- ck_in=>fifockin,
- ck_out=>fifockout,
- purge=>fifopurge
- );
-
-fifockin<=csData and clk and not rw;
-fifockout<=txready and not fifoempty
-fifopurge<=confreg(3) or rst;
-
-flagreg(0)<=fifoLI1;
-flagreg(1)<=fifoLI0;
-flagreg(2)<=fifoAFull;
-flagreg(3)<=fifoAEmpty;
-flagreg(4)<=fifoFull;
-flagreg(5)<=fifoEmpty;
-
-minirq<=fifoAFull and confreg(2) --fifo almost full AND Int/En
-
-TX1 : TXMIT
- port map(
- MCLKX16=>txck,
- WRITE=>'1',
- RESET => rst,
- DATA inter_data,
- TX => txout,
- TXRDY => txready
- );
-end TXMIT;
-
-
-geneck<=confreg(4) and masterck; -- On/Off et masterck
-
-CLOCK1 : clockgene
- port map(
- ckin=geneck,
- ckout=>txck,
- param=>confreg(1 downto 0)
- );
-
-
--- Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0)
-RCONF : regIO
- generic map(adr=>A_CONFIG)
- port map(
- bus_address=>bus_address,
- bus_data=>bus_data,
- input=>(others => '0'),
- output=>confreg,
- rw=>rw,
- load=>'0',
- ck=>clk,
- rst=>rst
- );
-
--- Flag : (x ! x ! Empty ! Full/Int ! FLI3 ! FLI2 ! FLI1 ! FLI0)
-RFLAG : regIO
- generic map(adr=>A_FLAG)
- port map(
- bus_address=>bus_address,
- bus_data=>bus_data,
- input=>flagreg,
- output=>open,
- rw=>rw,
- load=>'1',
- ck=>clk,
- rst=>rst
- );
-
-end rtl;
-
-
-
-
-
-
-