summaryrefslogtreecommitdiff
path: root/2004/n/fpga/src/portserie/txserie.vhd
blob: ee76e521041d1190f0840e4e80abd640ec868975 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
-- txserie.vhd
-- Eurobot 2004 : APB Team
-- Auteur : Pierre Prot

-- -------------------------------------------
-- Port s�rie TX pour le fpga robot
-- -------------------------------------------
-- 
-- * Prend 3 adresses m�moire :
--    0 - Txdata 
--    1 - Flag : (x ! x ! x ! x ! Empty ! Full/Int ! FLI1 ! FLI0)
--    2 - Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0)
-- * Mettre le bit On/Off � 1 pour activer la transmission
-- * Chaque �criture dans txdata charge la donn�e dans la fifo
-- * D�s que le registre � d�calage est vide, il enl�ve le dernier �l�ment de
--   la fifo et le transmet
-- * Deux bits de stop
-- * Quand la fifo est pleine, met le flag Full/Int � 1 et g�n�re une
--   interruption. Il faut alors mettre � 0 le bit IntEn, qui sera remis � 1 �
--   la prochaine �criture dans la fifo
-- * On peut lire l'�tat de la pile dans le registre de flags
-- * On peut vider la pile en mettant Purge � 1
-- * Baudrate disponible : 
--	BdR1/0 	! Baudrate
--	00	! 9600
--	01	! 19200
--	10	! 57600
--	11	! 115200



library ieee;
use	ieee.std_logic_1164.all;
use     ieee.std_logic_arith.all;
use     ieee.std_logic_unsigned.all;

use	work.nono_const.all;

entity txserie is
    port (
	rst : in std_logic;
	clk : in std_logic;
	rw  : in std_logic; -- read (0) / write (1)
	bus_data : inout T_DATA;
	masterck: in std_logic;
	txout:	out std_logic;
	minIRQ:	out std_logic
	
	csData : in std_logic;
	csConfig : in std_logic;
	csFlag : in std_logic;
    );
end txserie;

architecture rtl of txserie is

component regIO
    port(
	cs: in std_logic;
	bus_data: inout T_DATA;
	input: 	in   T_DATA;
	output: out  T_DATA;
	rw:	in std_logic;
	load:	in std_logic;
	ck:	in std_logic;
	rst:	in std_logic
	);
end component;


component fifo is
    port(
	data_in: in T_DATA;
	data_out: out T_DATA;
	ck: 	in std_logic;
	ck_in: 	in std_logic;
	ck_out:	in std_logic;
	flags:	out std_logic_vector(5 downto 0);
	purge:	in std_logic
	);
end component;


entity TXMIT is
   port (
         MCLKX16 : in  std_logic;
         WRITE   : in  std_logic;
         RESET   : in  std_logic;
	 DATA    : in  std_logic_vector(7 downto 0);

	 TX      : out std_logic;
	 TXRDY   : out std_logic
	 );
end TXMIT;

component clockgene
    port(
	ckin:	in std_logic;
	ckout:	out std_logic;
	param:	in std_logic_vector(1 downto 0)
	);
end component;

component decoder
    generic(adr : T_ADDRESS);
    port(
	bus_address: in T_DATA;
	cs:	out   std_logic
	);
end component;


signal fifoEmpty: std_logic;
signal fifoFull: std_logic;
signal fifoLI1: std_logic;
signal fifoLI0: std_logic;
--signal BdR1: std_logic;
--signal BdR0: std_logic;
signal fifopurge: std_logic:='0';
signal fifoflags: std_logic_vector(5 downto 0);
signal fifockin: std_logic;
signal fifockout: std_logic;

signal txck: std_logic;
signal confreg: T_DATA;
signal flagreg: T_DATA:="00000000";
signal inter_data: T_DATA;
signal txready: std_logic:='1';

begin
FIFO1: fifo
    port map(
	data_in=>bus_data,
	data_out=>inter_data,
	ck_in=>fifockin,
	ck_out=>fifockout,
	purge=>fifopurge
	);
	
fifockin<=csData and clk and not rw;
fifockout<=txready and not fifoempty
fifopurge<=confreg(3) or rst;

flagreg(0)<=fifoLI1;
flagreg(1)<=fifoLI0;
flagreg(2)<=fifoAFull;
flagreg(3)<=fifoAEmpty;
flagreg(4)<=fifoFull;
flagreg(5)<=fifoEmpty;

minirq<=fifoAFull and confreg(2) --fifo almost full AND Int/En

TX1 : TXMIT
    port map(
        MCLKX16=>txck,
        WRITE=>'1',
        RESET => rst,
	DATA inter_data,
	TX => txout,
	TXRDY => txready
	);
end TXMIT;


geneck<=confreg(4) and masterck; -- On/Off et masterck

CLOCK1 : clockgene
     port map(
	ckin=geneck,
	ckout=>txck,
	param=>confreg(1 downto 0)
	);


-- Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0)
RCONF : regIO
    generic map(adr=>A_CONFIG)
    port map(
	bus_address=>bus_address,
	bus_data=>bus_data,
	input=>(others => '0'),
	output=>confreg,
	rw=>rw,
	load=>'0',
	ck=>clk,
	rst=>rst
	);

-- Flag : (x ! x ! Empty ! Full/Int ! FLI3 ! FLI2 ! FLI1 ! FLI0)
RFLAG : regIO
    generic map(adr=>A_FLAG)
    port map(
	bus_address=>bus_address,
	bus_data=>bus_data,
	input=>flagreg,
	output=>open,
	rw=>rw,
	load=>'1',
	ck=>clk,
	rst=>rst
	);
    
end rtl;