summaryrefslogtreecommitdiff
path: root/2004/n/fpga/src/registre
diff options
context:
space:
mode:
authorgalmes2004-03-18 09:50:49 +0000
committergalmes2004-03-18 09:50:49 +0000
commit0213d3145f743a12e13b5b7602f0614e444a36a7 (patch)
tree9c45434a29ba6e2ca00a91b317473e1f4a9c91ec /2004/n/fpga/src/registre
parent07eed316dd59d665e3c29659dbbac9237d7defbe (diff)
Les fichiers sont synthétysables, bien qu'il me reste des doutes pour savoir
si tout fonctionne vraiment sans problèmes.
Diffstat (limited to '2004/n/fpga/src/registre')
-rw-r--r--2004/n/fpga/src/registre/bch_reg_rw.vhd4
-rw-r--r--2004/n/fpga/src/registre/reg_rw.vhd12
2 files changed, 12 insertions, 4 deletions
diff --git a/2004/n/fpga/src/registre/bch_reg_rw.vhd b/2004/n/fpga/src/registre/bch_reg_rw.vhd
index 07b7cc2..f42b090 100644
--- a/2004/n/fpga/src/registre/bch_reg_rw.vhd
+++ b/2004/n/fpga/src/registre/bch_reg_rw.vhd
@@ -36,6 +36,8 @@ architecture sim1 of bch_reg_rw is
signal data : T_DATA;
signal data_out : T_DATA;
+ constant CK_PERIOD : time := 10 ns;
+
begin
U1 : reg_rw port map (
clk => clk,
@@ -53,7 +55,7 @@ begin
'0' after 3*CK_PERIOD,
'1' after 5*CK_PERIOD,
'0' after 6*CK_PERIOD;
- rw <= '1', '0' after 3*CK_PERIOD;
+ rw <= ISA_WRITE, ISA_READ after 3*CK_PERIOD;
data <= x"01",
x"02" after 3*CK_PERIOD,
"ZZZZZZZZ" after 5*CK_PERIOD;
diff --git a/2004/n/fpga/src/registre/reg_rw.vhd b/2004/n/fpga/src/registre/reg_rw.vhd
index 32e940e..6b1c818 100644
--- a/2004/n/fpga/src/registre/reg_rw.vhd
+++ b/2004/n/fpga/src/registre/reg_rw.vhd
@@ -39,16 +39,22 @@ begin
-- reset
if (rst = '1') then
REG <= (others => '0');
+ data <= (others => 'Z');
-- écriture des données.
- elsif (clk'event and clk = '1') then
+ elsif (clk'event and clk = '1') then
if (enable = '1' and rw = ISA_WRITE) then
REG <= data;
+ else
+ if (enable = '1' and rw = ISA_READ) then
+ data <= REG;
+ else
+ data <= (others =>'Z');
+ end if;
end if;
end if;
- end process;
+ end process;
-- partie combinatoire.
- data <= REG when (enable = '1' and rw = ISA_READ) else (others => 'Z');
data_out <= REG;
end RTL;