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authorgalmes2004-03-18 09:50:49 +0000
committergalmes2004-03-18 09:50:49 +0000
commit0213d3145f743a12e13b5b7602f0614e444a36a7 (patch)
tree9c45434a29ba6e2ca00a91b317473e1f4a9c91ec /2004/n/fpga/src
parent07eed316dd59d665e3c29659dbbac9237d7defbe (diff)
Les fichiers sont synthétysables, bien qu'il me reste des doutes pour savoir
si tout fonctionne vraiment sans problèmes.
Diffstat (limited to '2004/n/fpga/src')
-rw-r--r--2004/n/fpga/src/gpio/gpio.vhd10
-rw-r--r--2004/n/fpga/src/gpio/gpio_it_detect.vhd35
-rw-r--r--2004/n/fpga/src/registre/bch_reg_rw.vhd4
-rw-r--r--2004/n/fpga/src/registre/reg_rw.vhd12
-rw-r--r--2004/n/fpga/src/three-state/tristate.vhd19
5 files changed, 61 insertions, 19 deletions
diff --git a/2004/n/fpga/src/gpio/gpio.vhd b/2004/n/fpga/src/gpio/gpio.vhd
index b85d5da..7ada162 100644
--- a/2004/n/fpga/src/gpio/gpio.vhd
+++ b/2004/n/fpga/src/gpio/gpio.vhd
@@ -66,6 +66,8 @@ end component;
-- Composant three-state.
component tristate is
port (
+ rst : std_logic;
+ clk : std_logic;
enable : in std_logic;
data_in : in T_DATA;
data_out : out T_DATA
@@ -78,6 +80,7 @@ end component;
signal bus_direction_mask : T_DATA;
signal bus_it_mask : T_DATA;
signal bus_reg_data : T_DATA;
+signal rst_it : std_logic;
begin
@@ -119,6 +122,8 @@ port map (
--
read_output : tristate
port map (
+ rst,
+ clk_i,
cs_read_output,
io_output,
bus_data
@@ -132,11 +137,14 @@ port map (
io_output
);
+-- signal intermédiaire.
+rst_it <= rst or cs_read_output;
+
--
it_detector : gpio_it_detect
port map (
clk_m,
- rst,
+ rst_it,
io_output,
bus_it_mask,
interrupt
diff --git a/2004/n/fpga/src/gpio/gpio_it_detect.vhd b/2004/n/fpga/src/gpio/gpio_it_detect.vhd
index 003c00d..f56e766 100644
--- a/2004/n/fpga/src/gpio/gpio_it_detect.vhd
+++ b/2004/n/fpga/src/gpio/gpio_it_detect.vhd
@@ -7,6 +7,10 @@
-- masque : si bit à 1 => on détecte l'interruption.
-- si bit à 0 => on détecte pas l'interruption.
+--ATTENTION : On prendra soin de faire dureer le it_mask à 0
+-- au moins 1 cycle, sinon, on aura une interruption au début !!!
+-- ICI j'ai encore des soucis...
+
library ieee;
use ieee.std_logic_1164.all;
@@ -32,29 +36,36 @@ architecture RTL of gpio_it_detect is
-- constant IT_ENABLE : std_logic := '1';
-- Signal interne
signal state_p : T_DATA; -- etat passe
-
+
begin
+
-- process séquentiel
process (rst, clk)
begin
- if (rst = '1') then
+ if (rst = '1') then
-- ne pas déclencher d'it après rst.
state_p <= data_in;
it_detected <= '0';
- elsif (clk'event and clk = '1') then
- -- TODO : Ajouter la synchronisation ??????? Pas besoin, non ?????
-
- if (data_in /= state_p) then
+ elsif (clk'event and clk = '1') then
+
+ if (state_p /= data_in) then
-- bit ayant droit de générer une interruption ?
if (((data_in xor state_p) and it_mask) /= x"00") then
- -- on émet le signal d'interruption.
- it_detected <= '1';
- end if;
- else
- it_detected <= '0';
+ -- on émet le signal d'interruption.
+ it_detected <= '1';
+ end if;
end if;
state_p <= data_in;
- end if;
+ end if;
end process;
+-- process (data_in)
+-- begin
+-- if (((data_in xor state_p) and it_mask) /= x"00") then
+ -- on émet le signal d'interruption.
+-- it_detected <= '1';
+-- end if;
+-- end process;
+
+
end RTL;
diff --git a/2004/n/fpga/src/registre/bch_reg_rw.vhd b/2004/n/fpga/src/registre/bch_reg_rw.vhd
index 07b7cc2..f42b090 100644
--- a/2004/n/fpga/src/registre/bch_reg_rw.vhd
+++ b/2004/n/fpga/src/registre/bch_reg_rw.vhd
@@ -36,6 +36,8 @@ architecture sim1 of bch_reg_rw is
signal data : T_DATA;
signal data_out : T_DATA;
+ constant CK_PERIOD : time := 10 ns;
+
begin
U1 : reg_rw port map (
clk => clk,
@@ -53,7 +55,7 @@ begin
'0' after 3*CK_PERIOD,
'1' after 5*CK_PERIOD,
'0' after 6*CK_PERIOD;
- rw <= '1', '0' after 3*CK_PERIOD;
+ rw <= ISA_WRITE, ISA_READ after 3*CK_PERIOD;
data <= x"01",
x"02" after 3*CK_PERIOD,
"ZZZZZZZZ" after 5*CK_PERIOD;
diff --git a/2004/n/fpga/src/registre/reg_rw.vhd b/2004/n/fpga/src/registre/reg_rw.vhd
index 32e940e..6b1c818 100644
--- a/2004/n/fpga/src/registre/reg_rw.vhd
+++ b/2004/n/fpga/src/registre/reg_rw.vhd
@@ -39,16 +39,22 @@ begin
-- reset
if (rst = '1') then
REG <= (others => '0');
+ data <= (others => 'Z');
-- écriture des données.
- elsif (clk'event and clk = '1') then
+ elsif (clk'event and clk = '1') then
if (enable = '1' and rw = ISA_WRITE) then
REG <= data;
+ else
+ if (enable = '1' and rw = ISA_READ) then
+ data <= REG;
+ else
+ data <= (others =>'Z');
+ end if;
end if;
end if;
- end process;
+ end process;
-- partie combinatoire.
- data <= REG when (enable = '1' and rw = ISA_READ) else (others => 'Z');
data_out <= REG;
end RTL;
diff --git a/2004/n/fpga/src/three-state/tristate.vhd b/2004/n/fpga/src/three-state/tristate.vhd
index 07e440e..d3616f7 100644
--- a/2004/n/fpga/src/three-state/tristate.vhd
+++ b/2004/n/fpga/src/three-state/tristate.vhd
@@ -18,6 +18,8 @@ use work.nono_const.all;
entity tristate is
port (
+ rst : std_logic;
+ clk : std_logic;
enable : in std_logic;
data_in : in T_DATA;
data_out : out T_DATA
@@ -26,6 +28,19 @@ end entity;
architecture RTL of tristate is
begin
- -- partie combinatoire.
- data_out <= data_in when (enable = '1') else (others => 'Z');
+ process (rst, clk)
+ begin
+ if (rst = '1') then
+ data_out <= (others => 'Z');
+ elsif (clk'event and clk = '1') then
+ if (enable = '1') then
+ data_out <= data_in;
+ else
+ data_out <= (others => 'Z');
+ end if;
+ end if;
+ end process;
+
+ -- partie combinatoire.
+ --data_out <= data_in when (enable = '1') else (others => 'Z');
end RTL;