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authorprot2004-02-24 20:32:14 +0000
committerprot2004-02-24 20:32:14 +0000
commitc2a15e687939510193db02700480cac678cae1aa (patch)
tree91b88b025d1055889c0a82318d73c42514b67d83 /2004/n/fpga/src/registre/test_reg.vhd
parent513b74008aa84ec83bc62e242d2ed75ea9444564 (diff)
Unsigned -> T_DATA et T_ADDRESS
Diffstat (limited to '2004/n/fpga/src/registre/test_reg.vhd')
-rw-r--r--2004/n/fpga/src/registre/test_reg.vhd28
1 files changed, 13 insertions, 15 deletions
diff --git a/2004/n/fpga/src/registre/test_reg.vhd b/2004/n/fpga/src/registre/test_reg.vhd
index 7573ba4..934a939 100644
--- a/2004/n/fpga/src/registre/test_reg.vhd
+++ b/2004/n/fpga/src/registre/test_reg.vhd
@@ -10,29 +10,27 @@ use ieee.std_logic_unsigned.all;
use work.nono_const.all;
entity testreg is
-constant adr_w : integer :=10;
-constant data_w : integer :=8;
end testreg;
architecture sim1 of testreg is
component regIO
- generic(adr:unsigned);
+ generic(adr:T_ADDRESS);
port(
- bus_data: inout unsigned ((NB_BIT_DATA - 1) downto 0);
- bus_address: in unsigned ((NB_BIT_ADDRESS - 1) downto 0);
- input: in unsigned((data_w - 1) downto 0);
- output: out unsigned((data_w - 1) downto 0);
- rw: in std_logic;
- load: in std_logic;
- ck: in std_logic;
- rst: in std_logic
+ bus_data: inout T_DATA;
+ bus_address: in T_ADDRESS;
+ input: in T_DATA;
+ output: out T_DATA;
+ rw: in std_logic;
+ load: in std_logic;
+ ck: in std_logic;
+ rst: in std_logic
);
end component;
-signal bus_address: unsigned((adr_w - 1) downto 0):="0000000000";
-signal bus_data: unsigned((data_w - 1) downto 0):="00000000";
-signal input: unsigned((data_w - 1) downto 0):="00000000";
-signal output: unsigned((data_w - 1) downto 0);
+signal bus_address: T_ADDRESS:="0000000000";
+signal bus_data: T_DATA:="00000000";
+signal input: T_DATA:="00000000";
+signal output: T_DATA;
signal rw: std_logic:='0';
signal load: std_logic:='0';
signal ck: std_logic:='0';