summaryrefslogtreecommitdiff
path: root/2004/n
diff options
context:
space:
mode:
authorprot2004-02-24 20:32:14 +0000
committerprot2004-02-24 20:32:14 +0000
commitc2a15e687939510193db02700480cac678cae1aa (patch)
tree91b88b025d1055889c0a82318d73c42514b67d83 /2004/n
parent513b74008aa84ec83bc62e242d2ed75ea9444564 (diff)
Unsigned -> T_DATA et T_ADDRESS
Diffstat (limited to '2004/n')
-rw-r--r--2004/n/fpga/src/registre/isa_const.vhd27
-rw-r--r--2004/n/fpga/src/registre/nono_const.vhd52
-rw-r--r--2004/n/fpga/src/registre/registre.vhd15
-rw-r--r--2004/n/fpga/src/registre/test_reg.vhd28
4 files changed, 21 insertions, 101 deletions
diff --git a/2004/n/fpga/src/registre/isa_const.vhd b/2004/n/fpga/src/registre/isa_const.vhd
index 12ab384..e69de29 100644
--- a/2004/n/fpga/src/registre/isa_const.vhd
+++ b/2004/n/fpga/src/registre/isa_const.vhd
@@ -1,27 +0,0 @@
--- isa_const.vhd
--- Eurobot 2004 : APB Team
--- Auteur : Pierre-André Galmes
--- Fichier de déclaration de constantes.
-
--- RQ : pour une indentation bien sous vim :
--- 1 - ":set shiftwidth=4"
--- 2 - se placer sous "package nono_const is"
--- 3 - tapez : = puis shift+G
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-
--- Constantes relatives au bus ISA
-package isa_const is
-
- -- Temps d'une période d'horloge sur le bus ISA
- constant ISA_CK_PERIOD : time := 50 ns;
-
- -- Ligne RW : lecture et écriture
- constant ISA_READ : std_logic := '0';
- constant ISA_WRITE : std_logic := '1';
-end isa_const;
-
diff --git a/2004/n/fpga/src/registre/nono_const.vhd b/2004/n/fpga/src/registre/nono_const.vhd
index 5c2e04a..e69de29 100644
--- a/2004/n/fpga/src/registre/nono_const.vhd
+++ b/2004/n/fpga/src/registre/nono_const.vhd
@@ -1,52 +0,0 @@
--- nono_const.vhd
--- Eurobot 2004 : APB Team
--- Auteur : Pierre-André Galmes
--- Fichier de déclaration de constantes.
-
--- RQ : pour une indentation bien sous vim :
--- 1 - ":set shiftwidth=4"
--- 2 - se placer sous "package nono_const is"
--- 3 - tapez : = puis shift+G
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-package nono_const is
-
- -- Temps d'une période d'horloge
- constant CK_PERIOD : time := 10 ns;
-
- -- Taille d'une addresse sur la carte
- -- RQ : 10 = nb suffisant
- -- 12 = 3 digit en héxa
- constant NB_BIT_ADDRESS : integer := 10;
-
- -- Taille des données sur la carte
- constant NB_BIT_DATA : integer := 8;
-
- -- Définition d'un nouveau type : ADDRESS
- subtype T_ADDRESS is unsigned ((NB_BIT_ADDRESS - 1) downto 0);
-
- -- Les différentes banques d'adresses (4 x 256)
- -- Rq pour Pierre : ça va influer sur le bloc de gestion du bus
- constant START_ADDR_B0 : T_ADDRESS := "0000000000";
- constant START_ADDR_B1 : T_ADDRESS := "0100000000";
- constant START_ADDR_B2 : T_ADDRESS := "1000000000";
- constant START_ADDR_B3 : T_ADDRESS := "1100000000";
-
- -- Les addresses des différents registres.
-
- -- gestion des interruptions
- constant A_INTERRUPT_MANAGER : T_ADDRESS := START_ADDR_B0 + x"00";
- -- Bloc d'IO
- constant A_REG_IO_DIRECTION : T_ADDRESS := START_ADDR_B0 + x"01";
- constant A_REG_IO_DATA : T_ADDRESS := START_ADDR_B0 + x"02";
- constant A_REG_IO_INTERRUPT_MASK : T_ADDRESS := START_ADDR_B0 + x"03";
- -- Bloc port série
- -- Bloc caméra
- -- Bloc PWM
- -- Bloc I²C
- -- Bloc servo-moteurs
-end nono_const;
diff --git a/2004/n/fpga/src/registre/registre.vhd b/2004/n/fpga/src/registre/registre.vhd
index 23a0079..94be6c2 100644
--- a/2004/n/fpga/src/registre/registre.vhd
+++ b/2004/n/fpga/src/registre/registre.vhd
@@ -30,12 +30,12 @@ use ieee.std_logic_unsigned.all;
use work.nono_const.all;
entity regIO is
- generic(adr : unsigned);
+ generic(adr : T_ADDRESS);
port(
- bus_data: inout unsigned ((NB_BIT_DATA - 1) downto 0);
- bus_address: in unsigned ((NB_BIT_ADDRESS - 1) downto 0);
- input: in unsigned(7 downto 0);
- output: out unsigned(7 downto 0);
+ bus_data: inout T_DATA;
+ bus_address: in T_ADDRESS;
+ input: in T_DATA;
+ output: out T_DATA;
rw: in std_logic;
load: in std_logic;
ck: in std_logic;
@@ -45,7 +45,7 @@ end entity;
architecture rtl of regIO is
-signal REG : unsigned((NB_BIT_DATA - 1) downto 0):=(others => '1');
+signal REG : T_DATA :=(others => '1');
begin
p_w:process(ck,load,input,rst)
@@ -67,7 +67,7 @@ begin
end if;
-- chargement : prioritaire sur l'écriture via le bus
- if(load='1') then
+ if(load='1' and not(ck='1' and rw='1')) then
REG<=input;
end if;
@@ -103,3 +103,4 @@ end rtl;
+
diff --git a/2004/n/fpga/src/registre/test_reg.vhd b/2004/n/fpga/src/registre/test_reg.vhd
index 7573ba4..934a939 100644
--- a/2004/n/fpga/src/registre/test_reg.vhd
+++ b/2004/n/fpga/src/registre/test_reg.vhd
@@ -10,29 +10,27 @@ use ieee.std_logic_unsigned.all;
use work.nono_const.all;
entity testreg is
-constant adr_w : integer :=10;
-constant data_w : integer :=8;
end testreg;
architecture sim1 of testreg is
component regIO
- generic(adr:unsigned);
+ generic(adr:T_ADDRESS);
port(
- bus_data: inout unsigned ((NB_BIT_DATA - 1) downto 0);
- bus_address: in unsigned ((NB_BIT_ADDRESS - 1) downto 0);
- input: in unsigned((data_w - 1) downto 0);
- output: out unsigned((data_w - 1) downto 0);
- rw: in std_logic;
- load: in std_logic;
- ck: in std_logic;
- rst: in std_logic
+ bus_data: inout T_DATA;
+ bus_address: in T_ADDRESS;
+ input: in T_DATA;
+ output: out T_DATA;
+ rw: in std_logic;
+ load: in std_logic;
+ ck: in std_logic;
+ rst: in std_logic
);
end component;
-signal bus_address: unsigned((adr_w - 1) downto 0):="0000000000";
-signal bus_data: unsigned((data_w - 1) downto 0):="00000000";
-signal input: unsigned((data_w - 1) downto 0):="00000000";
-signal output: unsigned((data_w - 1) downto 0);
+signal bus_address: T_ADDRESS:="0000000000";
+signal bus_data: T_DATA:="00000000";
+signal input: T_DATA:="00000000";
+signal output: T_DATA;
signal rw: std_logic:='0';
signal load: std_logic:='0';
signal ck: std_logic:='0';