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authorgafan2004-04-09 08:16:57 +0000
committergafan2004-04-09 08:16:57 +0000
commitc467982a69ddbb2575a02ccae987877f33d26fde (patch)
treecb78190d403db8eb484d971731ad255ba3190880 /2004/n/fpga/src/pwm/toppwm3.vhd
parentcdd43206764177ad7e16d32f47ff37d28c0221a6 (diff)
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Diffstat (limited to '2004/n/fpga/src/pwm/toppwm3.vhd')
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diff --git a/2004/n/fpga/src/pwm/toppwm3.vhd b/2004/n/fpga/src/pwm/toppwm3.vhd
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+--LIBRARIES SUCCEPTIBLES D'ETRE UTILISEES
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+--library work;
+library synopsys;
+use synopsys.bv_arithmetic.all;
+
+--ENTITY
+entity toppwm3 is
+port( RST :in std_logic;
+ CLK :in std_logic;
+ DATA :in std_logic_vector (7 downto 0);
+ OUTPWM :out std_logic
+ );
+end toppwm3;
+
+--CONSTANT
+
+--ARCHITECTURE
+architecture RTL of toppwm3 is
+--LES COMPONENTS
+--sequenceur fsm
+component fsmpwm3 is
+ port(
+ RST :in std_logic;
+ CLK :in std_logic;
+ CLK1USFSM :in std_logic;
+ tcfsm :in integer range 0 to 20161;
+ enloadfsm :out std_logic
+ );
+end component;
+--generateur d'horloge a 1 us
+component clk1us is
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ CLK1USOUT : out std_logic
+ );
+end component;
+--registre de stabilité des données
+component regdata3
+ port(
+ RST :in std_logic;
+ CLK :in std_logic;
+ CLK1USREG :in std_logic;
+ enloadreg :in std_logic;
+ datain :in std_logic_vector (7 downto 0);
+ datareg :out integer range 0 to 255--signaux de sortie du registre
+ );
+end component;
+--compteur
+component comptvalue3
+ port(
+ RST :in std_logic;
+ CLK :in std_logic;
+ CLK1USCOMPT :in std_logic;
+ loadcompt :in std_logic;
+ datacompt :in integer range 0 to 255;
+ tccompt :buffer integer range 0 to 20161;
+ valuecompt :out integer range 0 to 1000000
+ );
+end component ;
+--afficheur de sortie
+component affichepwm3
+ port(RST :in std_logic;
+ CLK :in std_logic;
+ CLK1USAFF :in std_logic;
+ valueaff :in integer range 0 to 1000000;
+ outpwm :out std_logic
+ );
+end component;
+
+--DECLARATION DES SIGNAUX LOCAUX
+-- sortie sequenceur
+signal enload_s :std_logic;
+--sortie horloge a 1 us
+signal clk1us_s : std_logic;
+--sortie du registre de stabilité des données
+signal datareg_s: integer range 0 to 255;
+-- sorties compteur
+signal tc_s : integer range 0 to 20161;
+signal value_s : integer range 0 to 1000000;
+--sortie afficheur
+
+begin
+--PORT MAP DES SIGNAUX INTERNES
+sequenceur3:fsmpwm3 port map(
+ RST=>RST,
+ CLK=>CLK,CLK1USFSM=>clk1us_s,
+ tcfsm=>tc_s,
+ enloadfsm=>enload_s
+ );
+horloge1us:clk1us port map(
+
+RST=>RST,
+CLK=>CLK,
+CLK1USOUT=>clk1us_s
+);
+registredata3:regdata3 port map(
+ RST=>RST,
+ CLK=>CLK,CLK1USREG=>clk1us_s,
+ enloadreg=>enload_s,
+ datain=>data,
+ datareg=>datareg_s
+ );
+
+compteurvaleur3:comptvalue3 port map(
+ RST=>RST,
+ CLK=>CLK,CLK1USCOMPT=>clk1us_s,
+ loadcompt=>enload_s,
+ datacompt=>datareg_s,
+ tccompt=>tc_s,
+ valuecompt=>value_s
+ );
+
+afficheur3: affichepwm3 port map(
+ RST=>RST,
+ CLK=>CLK,CLK1USAFF=>clk1us_s,
+ valueaff=>value_s,
+ outpwm=>outpwm
+ );
+
+end RTL;
+
+--configuration cf_toppwm3_rtl of toppwm3 is
+
+ --for RTL
+ --for sequenceur:fsm1 use entity WORK.fsm1(BEHAV);end for;
+ --for memory_j: regjp use entity WORK.regjp(BEHAV);end for;
+ --for memory_p: regjp use entity WORK.regjp(BEHAV);end for;
+ --for mux_j: mux164 use entity WORK.mux164(M164behav);end for;
+ --for mux_p: mux164 use entity WORK.mux164(M164behav);end for;
+ --for comp4couleur: comp4 use entity WORK.comp4(C4behav);end for;
+ --for comp2position: comp2 use entity WORK.comp2(C2behav);end for;
+ --for cnt4couleur: CPT4 use entity WORK.cpt4(BEHAV);end for;
+ --for cnt2position:CPT2 use entity WORK.cpt2(BEHAV);end for;
+ --end for;
+
+--end cf_toppwm3_rtl