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authorgafan2004-04-09 08:16:57 +0000
committergafan2004-04-09 08:16:57 +0000
commitc467982a69ddbb2575a02ccae987877f33d26fde (patch)
treecb78190d403db8eb484d971731ad255ba3190880 /2004/n
parentcdd43206764177ad7e16d32f47ff37d28c0221a6 (diff)
*** empty log message ***
Diffstat (limited to '2004/n')
-rw-r--r--2004/n/fpga/src/pwm/affichepwm3.vhd57
-rw-r--r--2004/n/fpga/src/pwm/clk1us.vhd47
-rw-r--r--2004/n/fpga/src/pwm/comptvalue3.vhd85
-rw-r--r--2004/n/fpga/src/pwm/fsmpwm3.vhd78
-rw-r--r--2004/n/fpga/src/pwm/regdata3.vhd47
-rw-r--r--2004/n/fpga/src/pwm/tb_affichepwm3.vhd62
-rw-r--r--2004/n/fpga/src/pwm/tb_clk1us.vhd49
-rw-r--r--2004/n/fpga/src/pwm/tb_comptvalue3.vhd71
-rw-r--r--2004/n/fpga/src/pwm/tb_fsmpwm3.vhd66
-rw-r--r--2004/n/fpga/src/pwm/tb_regdata3.vhd73
-rw-r--r--2004/n/fpga/src/pwm/tb_toppwm3.vhd83
-rw-r--r--2004/n/fpga/src/pwm/toppwm3.vhd141
12 files changed, 859 insertions, 0 deletions
diff --git a/2004/n/fpga/src/pwm/affichepwm3.vhd b/2004/n/fpga/src/pwm/affichepwm3.vhd
new file mode 100644
index 0000000..1462a61
--- /dev/null
+++ b/2004/n/fpga/src/pwm/affichepwm3.vhd
@@ -0,0 +1,57 @@
+-------------------------------------------------------------------------------
+--affichepwm3.vhd
+--Eurobot 2004 : APB Team
+--Auteur : Fidèle GAFAN
+--Registre à décalage affichantles signaux PWM
+--
+--REMARQUE(S):changer tccompt,q et valuecompt
+-- si CLK#32MHz et/ou qu'on modifie les valeurs de référence de T1
+-- et T2
+-- Tcmax=20ms/1us=20161cycles.
+--*Si DATACOMPT=0,on veut que T2 vale 0,5ms donc on initialise Q à la valeur
+--Q=0,5ms/1us=505.
+--*Si DATACOMPT=255,on veut que T2 vale 1,5ms donc on initialise Q à la valeur
+--Q=1,5ms/1us=1515.
+--*Pour toute autre valeur de DATACOMPT comprise entre les deux précédentes et
+--différentes de ces dernières,on initialise Q avec
+--Q=(0,5ms/1us)+(DATACOMPT*min[((1,5ms-0,5ms)/1us)/(255-1)]
+---------------------------------------------------------------------------------rtl de la sortie pwm en fonction de tc
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+--ENTITE
+entity affichepwm3 is
+ port ( RST : in std_logic;
+ CLK : in std_logic;
+ CLK1USAFF : in std_logic;
+ valueaff : in integer range 0 to 1000000;
+ outpwm : out std_logic
+ );
+end entity;
+--ARCHITECTURE
+architecture affichepwm3behav of affichepwm3 is
+
+begin
+ process(RST,CLK)
+ begin
+
+ if RST ='1' then
+ if (valueaff = 0)then
+ outpwm<='0';
+ elsif (valueaff /= 0) then
+ outpwm<='1';
+ end if;
+ elsif (clk'event and clk='1') then
+ if (CLK1USAFF='1') then
+ if (valueaff = 0)then
+ outpwm<='0';
+ elsif (valueaff /= 0) then
+ outpwm<='1';
+ end if;
+ end if;
+ end if;
+end process;
+end affichepwm3behav;
+
diff --git a/2004/n/fpga/src/pwm/clk1us.vhd b/2004/n/fpga/src/pwm/clk1us.vhd
new file mode 100644
index 0000000..082e4ec
--- /dev/null
+++ b/2004/n/fpga/src/pwm/clk1us.vhd
@@ -0,0 +1,47 @@
+-------------------------------------------------------------------------------
+--clk1us.vhd
+--Eurobot 2004 : APB Team
+--Auteur : Fidèle GAFAN
+--Module générateur d'horloge 1us-périodique(0,992us en réalité)
+--
+--REMARQUE(S):changer inc si CLK#32MHz
+--Les calculs ont été faits avec CLK=32MHz
+--donc 31*(1/CLK)=1us
+--d'où inc=31
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+--ENTITY
+entity clk1us is
+ port (
+ RST : in std_logic;
+ CLK : in std_logic; --32MHz
+ CLK1USOUT : out std_logic
+ );
+end entity;
+--ARCHITECTURE
+architecture clk1usbehav of clk1us is
+signal inc : integer range 0 to 31;-- nombres de cycles de clk necessaires
+ --pour 1us decremente
+begin
+ process(RST,CLK)
+ begin
+ if (RST = '1') then
+ CLK1USOUT<='0';
+ inc<=31; --31,25 normalement
+ elsif (CLK'event and CLK = '1') then
+ inc<=((inc)-1);
+ if (inc=30) then
+ CLK1USOUT<='1';
+ else
+ CLK1USOUT<='0';
+ if (inc=0) then
+ inc<=30;
+ end if;
+ end if;
+ end if;
+ end process;
+end clk1usbehav;
diff --git a/2004/n/fpga/src/pwm/comptvalue3.vhd b/2004/n/fpga/src/pwm/comptvalue3.vhd
new file mode 100644
index 0000000..0e32003
--- /dev/null
+++ b/2004/n/fpga/src/pwm/comptvalue3.vhd
@@ -0,0 +1,85 @@
+-------------------------------------------------------------------------------
+--comptvalue3.vhd
+--Eurobot 2004 : APB Team
+--Auteur : Fidèle GAFAN
+--Module générateur des PWM
+--
+--REMARQUE(S):changer tccompt,q et valuecompt
+-- si CLK#32MHz et/ou qu'on modifie les valeurs de référence de T1
+-- et T2
+-- Tcmax=20ms/1us=20161cycles.
+--*Si DATACOMPT=0,on veut que T2 vale 0,5ms donc on initialise Q à la valeur
+--Q=0,5ms/1us=505.
+--*Si DATACOMPT=255,on veut que T2 vale 1,5ms donc on initialise Q à la valeur
+--Q=1,5ms/1us=1515.
+--*Pour toute autre valeur de DATACOMPT comprise entre les deux précédentes et
+--différentes de ces dernières,on initialise Q avec
+--Q=(0,5ms/1us)+(DATACOMPT*min[((1,5ms-0,5ms)/1us)/(255-1)]
+-------------------------------------------------------------------------------
+--LIBRARY
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+--ENTITY
+entity comptvalue3 is
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ CLK1USCOMPT : in std_logic;
+ loadcompt : in std_logic;
+ datacompt : in integer range 0 to 255;
+ tccompt : buffer integer range 0 to 20161; --nb de cycles de clk1us
+ --pour avoir 19,999712ms
+ valuecompt : out integer range 0 to 1000000 --duree pdt laql la sortie
+ --reste haute. Decrementee
+ );
+end entity;
+
+architecture comptvalue3behav of comptvalue3 is
+
+ signal q : integer range 0 to 1000000; --recevra duree courante de valuecompt pdt laql la sortie
+ --reste haute. Decrementee
+
+begin
+ process(RST,CLK)
+constant tcmax :integer range 0 to 20161:=20161;
+ begin
+ if (RST = '1') then --initialisation horloge 19,999712ms et
+ --premier chargement sans load;role du
+ --state1.Prochain etat : calcul ie state3
+ tccompt<=tcmax;
+ if (datacompt=0) then
+ q<=505; --pour data=0 la periode doit durer 0,5ms
+ elsif (datacompt=255) then
+ q<=1515;--pour data=255 la periode doit durer 1,5ms
+ elsif((datacompt/=0)and (datacompt/=255)) then
+ q<=(505+(datacompt*3));
+ end if;
+ elsif (CLK'event and CLK = '1') then
+ if (CLK1USCOMPT='1') then
+ if (loadcompt = '1') then --state2 chargement pendant 1 clk1us
+ tccompt<=tcmax; --pdt 1 clk1us, tccompt reste max
+ if (datacompt=0) then
+ q<=505;--pour data=0 la periode doit durer 0,5ms
+ elsif (datacompt=255) then
+ q<=1515;--pour data=255 la periode doit durer 1,5ms
+ elsif ((datacompt/=0)and (datacompt/=255)) then
+ q<=(505+(datacompt*3));
+ end if;
+ elsif (loadcompt='0') then --state3 calculs a chaque front de clk1us
+ if (q/=0) then
+ q<=(q-1);
+ tccompt<=((tccompt)-1);
+ elsif (q=0) then
+ q<=0;
+ tccompt<=((tccompt)-1);
+ end if;
+ end if;--if du loadcompt
+ end if;--if du clk1us
+ end if;--elsif du clk et rst
+ end process;
+ valuecompt <= q;
+end comptvalue3behav;
+
+
diff --git a/2004/n/fpga/src/pwm/fsmpwm3.vhd b/2004/n/fpga/src/pwm/fsmpwm3.vhd
new file mode 100644
index 0000000..4776b30
--- /dev/null
+++ b/2004/n/fpga/src/pwm/fsmpwm3.vhd
@@ -0,0 +1,78 @@
+-------------------------------------------------------------------------------
+--fsmpwm3.vhd
+--Eurobot 2004 : APB Team
+--Auteur : Fidèle GAFAN
+--Séquenceur du module générateur des signaux de commande du servo-moteur
+--
+--REMARQUE(S):NADA
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+library work;
+library synopsys;
+use synopsys.bv_arithmetic.all;
+--ENTITY
+
+entity fsmpwm3 is
+port( RST :in std_logic;
+ CLK :in std_logic;
+ CLK1USFSM :in std_logic;
+ tcfsm :in integer range 0 to 20161;--synch des 20 ms
+ enloadfsm :out std_logic
+ );
+end fsmpwm3;
+
+
+--ARCHITECTURE
+architecture BEHAV of fsmpwm3 is
+
+type machine is (STATE1,STATE2, STATE3);
+ signal state_c,state_f : machine;
+begin
+
+ -- PROCESS COMBI
+ process(CLK1USFSM,tcfsm,state_c)
+constant tcmax :integer range 0 to 20161:= 20161;
+ begin
+ enloadfsm <='0';
+ state_f <= state_c;
+ case state_c is
+ when STATE1 => enloadfsm<='0'; --demarrage avec prem valeur de data
+ --sans necessite de load a 1:regdata
+ --sort 0
+ state_f<=STATE3; --passe a st3 dès front de clk1us
+ --pour calculs
+
+ when STATE2 => enloadfsm<='1'; --chargement pendant 1 cycle de
+ --clk1us et tc est max
+ state_f<=STATE3;
+ when STATE3 => enloadfsm<='0'; --calculs
+
+ if (tcfsm=0) then --test de fin de comptage des 20ms
+ state_f<=STATE2;
+ elsif ((tcfsm<=tcmax) and (tcfsm/=0)) then --continuer à compter jusqu'à 20ms
+ state_f<=STATE3;
+ elsif ((tcfsm>tcmax)) then
+ state_f<=STATE2;
+ end if;
+ when others => null;
+
+ end case;
+ end process;
+
+ -- PROCESS SEQ
+ process (RST,CLK)
+ begin
+ if (RST='1') then
+ state_c<=STATE1;
+ --enloadfsm<='0';--si mis, indéterminée !!!
+ elsif (CLK'event and CLK='1') then
+ if (CLK1USFSM='1') then
+ state_c <= state_f;
+ end if;end if;
+ end process;
+
+ end BEHAV;
+
diff --git a/2004/n/fpga/src/pwm/regdata3.vhd b/2004/n/fpga/src/pwm/regdata3.vhd
new file mode 100644
index 0000000..d3ccc1e
--- /dev/null
+++ b/2004/n/fpga/src/pwm/regdata3.vhd
@@ -0,0 +1,47 @@
+--*************************************************************
+--*regdata3.vhd *
+--*Eurobot 2004 : APB Team *
+--*Auteur : Fidèle GAFAN *
+--*Registre de *
+--* sauvegarde des donnees entrant *
+--* conversion des vecteurs en entiers *
+--* mise à disposition de cette donnée pour les autres modules*
+--*REMARQUE(S) *
+--*pour reset=1:le premier PWM fait 0,5ms *
+--*************************************************************
+--LIBRARIES
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+library work;
+library synopsys;
+use synopsys.bv_arithmetic.all;
+--ENTITY
+entity regdata3 is
+port( RST : in std_logic;
+ CLK : in std_logic;
+ CLK1USREG : in std_logic;--horloge se déclenchant toutes les 1us
+ enloadreg: in std_logic; --autorisation de chargement provenant de fsm
+ datain: in std_logic_vector (7 downto 0);
+ datareg: out integer range 0 to 255
+ );
+end regdata3;
+--ARCHITECTURE
+architecture BEHAV of regdata3 is
+begin
+process (RST,clk)
+begin
+if (RST='1') then
+ datareg<=0; --valeur par défaut de la sortie=0,5ms
+ --datareg<=conv_integer(std_logic_vector(datain (7 downto 0))); --à
+ --activer si on veut un démarrage immédiat
+elsif (CLK'event and CLK = '1') then
+ if (CLK1USREG='1') then --chargement toutes les 1us si load=1
+ if (enloadreg='1') then
+ datareg<=conv_integer(std_logic_vector(datain (7 downto 0)));
+ end if;
+ end if;
+end if;
+end process;
+end BEHAV;
diff --git a/2004/n/fpga/src/pwm/tb_affichepwm3.vhd b/2004/n/fpga/src/pwm/tb_affichepwm3.vhd
new file mode 100644
index 0000000..4a93b0a
--- /dev/null
+++ b/2004/n/fpga/src/pwm/tb_affichepwm3.vhd
@@ -0,0 +1,62 @@
+--rtl bench de la sortie pwm en fonction de tc test à faire sur41MS environ
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_arith.all;
+ use IEEE.std_logic_unsigned.all;
+library synopsys;
+use synopsys.bv_arithmetic.all;
+--ENTITY
+entity tb_affichepwm3 is
+end tb_affichepwm3;
+--ARCHITECTURE
+architecture sim1 of tb_affichepwm3 is
+ component affichepwm3
+ port(rst : in std_logic;
+ clk : in std_logic;
+ clk1usaff : in std_logic;
+ -- tcaff : in integer;
+ valueaff : in integer;
+ outpwm : out std_logic
+ );
+ end component;
+-- declaration des signaux
+signal clk : std_logic:='0';
+ signal clk1usaff : std_logic:='0';
+ signal rst : std_logic;
+signal tcaff: integer :=20161; --mettre a 20161
+signal valueaff: integer:=0;
+signal outpwm : std_logic;
+--declaration de constantes
+constant CLK1US_PERIOD :time:= 992 ns;
+constant tcmax :integer:= 20161; --pour le clk1us
+constant CLK_PERIOD :time := 32 ns ;
+
+begin
+ U1affichepwm3: affichepwm3 port map (
+ rst=>rst,clk=>clk,clk1usaff=>clk1usaff,
+ -- tcaff=>tcaff,
+ valueaff=>valueaff,
+ outpwm=>outpwm
+ );
+
+--STIMULI
+ rst<='1','0'after (CLK1US_PERIOD/3);
+ clk<= not clk after (CLK_PERIOD/2);
+ clk1usaff<= not clk1usaff after (CLK1US_PERIOD/2);
+--tcaff<=tcmax,0 after (tcmax*CLK1US_PERIOD),
+ --tcmax after (2*(tcmax*CLK1US_PERIOD)),
+ --0 after (3*(tcmax*CLK1US_PERIOD)),
+ --tcmax after (4*(tcmax*CLK1US_PERIOD));
+
+valueaff<= 0,90 after((tcmax*CLK1US_PERIOD)-(CLK1US_PERIOD/2)),
+ 0 after((tcmax*CLK1US_PERIOD)+(CLK1US_PERIOD*2)),
+ 12 after((2*(tcmax*CLK1US_PERIOD))-(CLK1US_PERIOD/2));
+end sim1;
+
+--CONFIGURATION
+configuration cfg_tb_affichepwm3 of tb_affichepwm3 is
+ for sim1
+ for all : affichepwm3 use entity work.affichepwm3(affichepwm3behav);
+ end for;
+end for;
+end cfg_tb_affichepwm3;
diff --git a/2004/n/fpga/src/pwm/tb_clk1us.vhd b/2004/n/fpga/src/pwm/tb_clk1us.vhd
new file mode 100644
index 0000000..03727e9
--- /dev/null
+++ b/2004/n/fpga/src/pwm/tb_clk1us.vhd
@@ -0,0 +1,49 @@
+--test bench du compteur sur value pour duree du niveau haut test à faire sur 59ms environ
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_arith.all;
+ use IEEE.std_logic_unsigned.all;
+library synopsys;
+use synopsys.bv_arithmetic.all;
+--ENTITY
+entity tb_clk1us is
+end tb_clk1us;
+--ARCHITECTURE
+architecture sim1 of tb_clk1us is
+ component clk1us
+ port(
+ rst : in std_logic;
+ clk : in std_logic;
+ --inc : buffer integer;
+ clk1usout : out std_logic
+ );
+ end component;
+-- declaration des signaux
+signal rst:std_logic;
+signal clk:std_logic:='0';
+--signal inc : integer;
+signal clk1usout : std_logic;
+--declaration de constantes
+constant CLK_PERIOD :time := 32 ns ; --31,25ns normalememt
+
+begin
+ U1clk1us: clk1us port map (
+rst=>rst,
+ clk=>clk,
+ -- inc=>inc,
+ clk1usout=>clk1usout
+ );
+
+--STIMULI
+ clk<= not clk after (CLK_PERIOD/2);
+ rst<='1','0' after (CLK_PERIOD/4);
+
+end sim1;
+
+--CONFIGURATION
+configuration cfg_tb_clk1us of tb_clk1us is
+ for sim1
+ for all : clk1us use entity work.clk1us(clk1usbehav);
+ end for;
+end for;
+end cfg_tb_clk1us;
diff --git a/2004/n/fpga/src/pwm/tb_comptvalue3.vhd b/2004/n/fpga/src/pwm/tb_comptvalue3.vhd
new file mode 100644
index 0000000..6247158
--- /dev/null
+++ b/2004/n/fpga/src/pwm/tb_comptvalue3.vhd
@@ -0,0 +1,71 @@
+--test bench du compteur sur value pour duree du niveau haut test à faire sur 59ms environ
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_arith.all;
+ use IEEE.std_logic_unsigned.all;
+library synopsys;
+use synopsys.bv_arithmetic.all;
+--ENTITY
+entity tb_comptvalue3 is
+end tb_comptvalue3;
+--ARCHITECTURE
+architecture sim1 of tb_comptvalue3 is
+ component comptvalue3
+ port(
+ rst : in std_logic;
+ clk : in std_logic;
+ clk1uscompt : in std_logic;
+ loadcompt : in std_logic;
+ datacompt : in integer;
+ tccompt : buffer integer;
+ valuecompt : out integer
+ );
+ end component;
+-- declaration des signaux
+signal rst:std_logic;
+signal clk:std_logic:='0';
+signal clk1uscompt: std_logic:='0';
+signal loadcompt: std_logic;
+signal datacompt : integer:=0;
+signal tccompt: integer;
+signal valuecompt: integer;
+--declaration de constantes
+
+constant CLK1US_PERIOD :time:= 992 ns;
+constant tcmax :integer:= 20161; --pour le clk1us
+constant CLK_PERIOD :time := 32 ns ;
+begin
+ U1comptvalue3: comptvalue3 port map (
+ rst=>rst,
+ clk=>clk,
+ clk1uscompt=>clk1uscompt,
+ loadcompt=>loadcompt,
+ datacompt=>datacompt,
+ tccompt=>tccompt,
+ valuecompt=>valuecompt
+ );
+
+--STIMULI
+ clk<= not clk after (CLK_PERIOD/2);rst<='1','0'after (CLK_PERIOD/6);
+ clk1uscompt<= not clk1uscompt after (CLK1US_PERIOD/2);
+ loadcompt<='0','1'after (tcmax*CLK1US_PERIOD-(CLK1US_PERIOD/2)),'0' after (tcmax*CLK1US_PERIOD+(CLK1US_PERIOD/2)),
+ '1'after((2*(tcmax*CLK1US_PERIOD))-(CLK1US_PERIOD/2)),'0' after ((2*(tcmax*CLK1US_PERIOD))+(CLK1US_PERIOD/2)),
+ '1'after ((3*(tcmax*CLK1US_PERIOD))-(CLK1US_PERIOD/2)),'0' after ((3*(tcmax*CLK1US_PERIOD))+(CLK1US_PERIOD/2)),
+ '1'after((4*(tcmax*CLK1US_PERIOD))-(CLK1US_PERIOD/2)),'0' after ((4*(tcmax*CLK1US_PERIOD))+(CLK1US_PERIOD/2));
+ datacompt<=
+ 0, 25 after ((tcmax*CLK1US_PERIOD)-(CLK1US_PERIOD/6)),
+ 0 after (2*(tcmax*CLK1US_PERIOD)-(CLK1US_PERIOD/6)),
+ 255 after (3*(tcmax*CLK1US_PERIOD)-(CLK1US_PERIOD/6)),
+ 100 after (4*(tcmax*CLK1US_PERIOD)-(CLK1US_PERIOD/6));
+
+
+end sim1;
+
+--CONFIGURATION
+configuration cfg_tb_comptvalue3 of tb_comptvalue3 is
+ for sim1
+ for all : comptvalue3 use entity work.comptvalue3(comptvalue3behav);
+ end for;
+end for;
+end cfg_tb_comptvalue3;
+
diff --git a/2004/n/fpga/src/pwm/tb_fsmpwm3.vhd b/2004/n/fpga/src/pwm/tb_fsmpwm3.vhd
new file mode 100644
index 0000000..aec67ed
--- /dev/null
+++ b/2004/n/fpga/src/pwm/tb_fsmpwm3.vhd
@@ -0,0 +1,66 @@
+--simulation pendant 41 ms
+
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_arith.all;
+ use IEEE.std_logic_unsigned.all;
+library work;
+library synopsys;
+use synopsys.bv_arithmetic.all;
+--ENTITY
+entity tb_fsmpwm3 is
+end tb_fsmpwm3;
+--ARCHITECTURE
+architecture sim1 of tb_fsmpwm3 is
+ component fsmpwm3
+ port(RST :in std_logic;
+ CLK :in std_logic;
+ CLK1USFSM :in std_logic;
+ tcfsm :in integer;
+
+ enloadfsm:out std_logic
+ );
+ end component;
+-- declaration des signaux
+signal RST:std_logic;
+signal CLK:std_logic:='0';
+signal CLK1USFSM:std_logic:='0';
+signal tcfsm:integer:=0;
+
+signal enloadfsm: std_logic:='0';
+
+--CONSTANT
+constant CLK1US_PERIOD :time:= 992 ns;
+constant tcmax :integer:= 20161; --pour le clk1us
+constant CLK_PERIOD :time := 32 ns ;
+--MAP
+ begin
+ U1fsmpwm3 : fsmpwm3 port map (
+ RST=>RST,CLK=>CLK,CLK1USFSM=>CLK1USFSM,tcfsm=>tcfsm,enloadfsm=>enloadfsm
+ );
+
+ rst<='1','0'after (CLK1US_PERIOD/3);
+ clk<= not clk after (CLK_PERIOD/2);
+ clk1usfsm<= not clk1usfsm after (CLK1US_PERIOD/2);
+-- STIMULI
+
+ process
+ begin
+ tcfsm<=tcmax;wait for (CLK1US_PERIOD);
+ tcfsm<=10;wait for ((tcmax*(CLK1US_PERIOD))-(CLK1US_PERIOD));
+ tcfsm<=0;wait for ((CLK1US_PERIOD));
+ tcfsm<=tcmax;wait for (CLK1US_PERIOD);
+ tcfsm<=10;wait for ((tcmax*(CLK1US_PERIOD))-(CLK1US_PERIOD));
+ tcfsm<=0;wait for ((CLK1US_PERIOD));
+
+ end process;
+end sim1;
+
+--CONFIGURATION
+configuration cfg_tb_fsmpwm3 of tb_fsmpwm3 is
+ for sim1
+ --for U1fsmpwm3 : fsmpwm3 use entity work.fsmpwm3(BEHAV);
+ for all: fsmpwm3 use entity work.fsmpwm3(BEHAV);
+end for;
+end for;
+end cfg_tb_fsmpwm3;
diff --git a/2004/n/fpga/src/pwm/tb_regdata3.vhd b/2004/n/fpga/src/pwm/tb_regdata3.vhd
new file mode 100644
index 0000000..90fd060
--- /dev/null
+++ b/2004/n/fpga/src/pwm/tb_regdata3.vhd
@@ -0,0 +1,73 @@
+--rtlBench du registre de sauvegarde des donnees entrantes:qst de stabilite
+--simul sur 41 ms
+--*******tests
+--on verifie si 099 est bien en sortie au depart alors que load vaut 0
+--si chq load dure 1 clk1us
+--si a chq nv haut de load, l'entree est sur la sortie.
+--***********
+
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_arith.all;
+ use IEEE.std_logic_unsigned.all;
+library work;
+library synopsys;
+use synopsys.bv_arithmetic.all;
+--ENTITY
+entity tb_regdata3 is
+end tb_regdata3;
+--ARCHITECTURE
+architecture sim1 of tb_regdata3 is
+ component regdata3
+ port(RST : in std_logic;
+ CLK : in std_logic;
+ clk1usreg : in std_logic;
+ enloadreg: in std_logic;
+ datain: in std_logic_vector (7 downto 0);
+ datareg: out integer--signaux de sortie du registre
+ );
+ end component;
+
+-- declaration des signaux
+signal rst: std_logic;
+signal clk: std_logic:='0';
+signal clk1usreg: std_logic:='0';
+signal enloadreg: std_logic:='0';
+
+signal datain: std_logic_vector (7 downto 0):="00000000";
+
+signal datareg: integer:=0;--signaux de sortie du registre
+
+--CONSTANT
+constant CLK1US_PERIOD :time:=992 ns;
+constant tcmax :integer:= 20161; --pour le clk1us
+constant CLK_PERIOD :time := 32 ns ;
+
+--MAP
+ begin
+ U1regdata3 : regdata3 port map (
+ rst=>rst,clk=>clk,clk1usreg=>clk1usreg,enloadreg=>enloadreg,datain=>datain,datareg=>datareg
+ );
+-- STIMULI
+ clk<= not clk after (CLK_PERIOD/2);
+ rst<='1','0' after (CLK_PERIOD/3);
+ clk1usreg<= not clk1usreg after (CLK1US_PERIOD/2);
+
+
+ enloadreg<= '0','1' after (tcmax*CLK1US_PERIOD), '0' after ((tcmax*CLK1US_PERIOD)+(CLK1US_PERIOD)),
+ '1' after(2*(tcmax*CLK1US_PERIOD)), '0' after ((2*(tcmax*CLK1US_PERIOD))+(CLK1US_PERIOD));
+
+
+ datain<="10100000","00000101" after (CLK1US_PERIOD/4),
+ "00011001" after((tcmax*CLK1US_PERIOD)-(CLK1US_PERIOD/6)),
+ "00000000" after((2*(tcmax*CLK1US_PERIOD))-(CLK1US_PERIOD/6));
+
+
+end sim1;
+--CONFIGURATION
+configuration cfg_tb_regdata3 of tb_regdata3 is
+ for sim1
+ for U1regdata3 : regdata3 use entity work.regdata3(BEHAV);
+end for;
+end for;
+end cfg_tb_regdata3;
diff --git a/2004/n/fpga/src/pwm/tb_toppwm3.vhd b/2004/n/fpga/src/pwm/tb_toppwm3.vhd
new file mode 100644
index 0000000..5775d18
--- /dev/null
+++ b/2004/n/fpga/src/pwm/tb_toppwm3.vhd
@@ -0,0 +1,83 @@
+--simulation sur 82 ms environ
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+library work;
+library synopsys;
+use synopsys.bv_arithmetic.all;
+
+--ENTITY
+entity tb_toppwm3 is
+end tb_toppwm3;
+
+--ARCHITECTURE
+architecture sim1 of tb_toppwm3 is
+ component toppwm3
+ port(
+ RST :in std_logic;
+ CLK :in std_logic;
+ DATA :in std_logic_vector (7 downto 0);
+ OUTPWM :out std_logic
+ );
+ end component;
+-- declaration des signaux
+signal RST : std_logic;
+signal CLK : std_logic:='0';
+signal DATA: std_logic_vector (7 downto 0);
+
+signal OUTPWM: std_logic;
+
+--CONSTANT
+--constant ENVLP_PERIOD : time := 20 ms;
+--constant DATA_MAX : integer := 15;
+--constant CLK_PERIOD : time := (ENVLP_PERIOD/DATA_MAX);
+--constant CLK1_FREQ :integer:= 30E+6;--car freq de 30MHz
+--constant tcmax :integer:= 600E3;
+--constant seconde :time := 1 sec;
+--constant CLK_PERIOD :time := (seconde/CLK1_FREQ) ;
+
+--constant CLK1US_PERIOD :time:= 992 ns;
+--constant tcmax :integer:= 20161; --pour le clk1us
+constant CLK_PERIOD :time := 32 ns ;
+
+
+--MAP
+ begin
+ U1toppwm3: toppwm3 port map (
+ RST=>RST,
+ CLK=>CLK,
+ DATA=>DATA,
+ OUTPWM=>OUTPWM
+ );
+
+-- STIMULI
+ RST <= '1','0' after(CLK_PERIOD/6);
+ clk<= not clk after (CLK_PERIOD/2);
+
+ data<="00000011", "00011001" after 17 ms, --0 25
+ -- "00000000", "00011001" after 17 ms, --0 25
+ "00000000" after 38 ms, -- 0
+ "11111111" after 58 ms, -- 255
+ "01111111" after 78 ms; -- 127
+
+ --"00000000", "00011001" after ((tcmax*CLK1US_PERIOD)-(CLK1US_PERIOD/6)),
+ --"00000000" after (2*(tcmax*CLK1US_PERIOD)-(CLK1US_PERIOD/6)),
+ --"11111111" after (3*(tcmax*CLK1US_PERIOD)-(CLK1US_PERIOD/6)),
+ --"00011100" after (4*(tcmax*CLK1US_PERIOD)-(CLK1US_PERIOD/6));
+
+ --"00000000",--10
+ -- "01100101" after 25 ms,--5
+ -- "00000000" after 30 ms,--vérifier que cette donnée est bien perdue
+ -- "11111111" after 38 ms,
+ -- "00100000" after 50 ms;
+end sim1;
+
+--CONFIGURATION
+configuration cfg_tb_toppwm3 of tb_toppwm3 is
+ for sim1
+ -- for U1toppwm3 : toppwm3 use entity work.toppwm3(RTL);end for;
+ for all : toppwm3 use entity work.toppwm3(RTL);end for;
+end for;
+end cfg_tb_toppwm3;
+
diff --git a/2004/n/fpga/src/pwm/toppwm3.vhd b/2004/n/fpga/src/pwm/toppwm3.vhd
new file mode 100644
index 0000000..60e8105
--- /dev/null
+++ b/2004/n/fpga/src/pwm/toppwm3.vhd
@@ -0,0 +1,141 @@
+--LIBRARIES SUCCEPTIBLES D'ETRE UTILISEES
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+--library work;
+library synopsys;
+use synopsys.bv_arithmetic.all;
+
+--ENTITY
+entity toppwm3 is
+port( RST :in std_logic;
+ CLK :in std_logic;
+ DATA :in std_logic_vector (7 downto 0);
+ OUTPWM :out std_logic
+ );
+end toppwm3;
+
+--CONSTANT
+
+--ARCHITECTURE
+architecture RTL of toppwm3 is
+--LES COMPONENTS
+--sequenceur fsm
+component fsmpwm3 is
+ port(
+ RST :in std_logic;
+ CLK :in std_logic;
+ CLK1USFSM :in std_logic;
+ tcfsm :in integer range 0 to 20161;
+ enloadfsm :out std_logic
+ );
+end component;
+--generateur d'horloge a 1 us
+component clk1us is
+ port (
+ RST : in std_logic;
+ CLK : in std_logic;
+ CLK1USOUT : out std_logic
+ );
+end component;
+--registre de stabilité des données
+component regdata3
+ port(
+ RST :in std_logic;
+ CLK :in std_logic;
+ CLK1USREG :in std_logic;
+ enloadreg :in std_logic;
+ datain :in std_logic_vector (7 downto 0);
+ datareg :out integer range 0 to 255--signaux de sortie du registre
+ );
+end component;
+--compteur
+component comptvalue3
+ port(
+ RST :in std_logic;
+ CLK :in std_logic;
+ CLK1USCOMPT :in std_logic;
+ loadcompt :in std_logic;
+ datacompt :in integer range 0 to 255;
+ tccompt :buffer integer range 0 to 20161;
+ valuecompt :out integer range 0 to 1000000
+ );
+end component ;
+--afficheur de sortie
+component affichepwm3
+ port(RST :in std_logic;
+ CLK :in std_logic;
+ CLK1USAFF :in std_logic;
+ valueaff :in integer range 0 to 1000000;
+ outpwm :out std_logic
+ );
+end component;
+
+--DECLARATION DES SIGNAUX LOCAUX
+-- sortie sequenceur
+signal enload_s :std_logic;
+--sortie horloge a 1 us
+signal clk1us_s : std_logic;
+--sortie du registre de stabilité des données
+signal datareg_s: integer range 0 to 255;
+-- sorties compteur
+signal tc_s : integer range 0 to 20161;
+signal value_s : integer range 0 to 1000000;
+--sortie afficheur
+
+begin
+--PORT MAP DES SIGNAUX INTERNES
+sequenceur3:fsmpwm3 port map(
+ RST=>RST,
+ CLK=>CLK,CLK1USFSM=>clk1us_s,
+ tcfsm=>tc_s,
+ enloadfsm=>enload_s
+ );
+horloge1us:clk1us port map(
+
+RST=>RST,
+CLK=>CLK,
+CLK1USOUT=>clk1us_s
+);
+registredata3:regdata3 port map(
+ RST=>RST,
+ CLK=>CLK,CLK1USREG=>clk1us_s,
+ enloadreg=>enload_s,
+ datain=>data,
+ datareg=>datareg_s
+ );
+
+compteurvaleur3:comptvalue3 port map(
+ RST=>RST,
+ CLK=>CLK,CLK1USCOMPT=>clk1us_s,
+ loadcompt=>enload_s,
+ datacompt=>datareg_s,
+ tccompt=>tc_s,
+ valuecompt=>value_s
+ );
+
+afficheur3: affichepwm3 port map(
+ RST=>RST,
+ CLK=>CLK,CLK1USAFF=>clk1us_s,
+ valueaff=>value_s,
+ outpwm=>outpwm
+ );
+
+end RTL;
+
+--configuration cf_toppwm3_rtl of toppwm3 is
+
+ --for RTL
+ --for sequenceur:fsm1 use entity WORK.fsm1(BEHAV);end for;
+ --for memory_j: regjp use entity WORK.regjp(BEHAV);end for;
+ --for memory_p: regjp use entity WORK.regjp(BEHAV);end for;
+ --for mux_j: mux164 use entity WORK.mux164(M164behav);end for;
+ --for mux_p: mux164 use entity WORK.mux164(M164behav);end for;
+ --for comp4couleur: comp4 use entity WORK.comp4(C4behav);end for;
+ --for comp2position: comp2 use entity WORK.comp2(C2behav);end for;
+ --for cnt4couleur: CPT4 use entity WORK.cpt4(BEHAV);end for;
+ --for cnt2position:CPT2 use entity WORK.cpt2(BEHAV);end for;
+ --end for;
+
+--end cf_toppwm3_rtl