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authorprot2004-02-25 20:00:21 +0000
committerprot2004-02-25 20:00:21 +0000
commit7de0fd178d7b2dbccbf34cbffda38a1f4bdb4583 (patch)
tree622aface1b103ce9c470457eb2f8496217874cac /2004/n/fpga/src/portserie
parentc50aca8c4be2ef778eb634df7a530cde2ff23f39 (diff)
fifo comportementale
Diffstat (limited to '2004/n/fpga/src/portserie')
-rw-r--r--2004/n/fpga/src/portserie/bch_txserie.vhd11
-rw-r--r--2004/n/fpga/src/portserie/decoder.vhd13
-rw-r--r--2004/n/fpga/src/portserie/fifo.vhd7
-rw-r--r--2004/n/fpga/src/portserie/fifodriver.vhd3
-rw-r--r--2004/n/fpga/src/portserie/portserie.sws5
-rw-r--r--2004/n/fpga/src/portserie/txserie.vhd29
6 files changed, 41 insertions, 27 deletions
diff --git a/2004/n/fpga/src/portserie/bch_txserie.vhd b/2004/n/fpga/src/portserie/bch_txserie.vhd
index f976ce3..735078d 100644
--- a/2004/n/fpga/src/portserie/bch_txserie.vhd
+++ b/2004/n/fpga/src/portserie/bch_txserie.vhd
@@ -67,13 +67,14 @@ begin
);
rst <= '1', '0' after CK_PERIOD;
- clk <= not clk after (CK_PERIOD/2);
+ clk <= not clk after (CK_PERIOD);
rw <= '0';
bus_address <= "0000000011",
- "0000000100" after 3*CK_PERIOD,
- "0000000010" after 5*CK_PERIOD;
+ "0000000100" after 6*CK_PERIOD,
+ "0000000100" after 10*CK_PERIOD,
+ "0000000011" after 16*CK_PERIOD;
bus_data <= "01010101";--) after 10 ns;
- masterck<= not masterck after (CK_PERIOD/3);
+ masterck<= not masterck after (CK_PERIOD/11);
end sim1;
@@ -85,3 +86,5 @@ end cf1_bch_txserie;
+
+
diff --git a/2004/n/fpga/src/portserie/decoder.vhd b/2004/n/fpga/src/portserie/decoder.vhd
index 920431d..ac586b6 100644
--- a/2004/n/fpga/src/portserie/decoder.vhd
+++ b/2004/n/fpga/src/portserie/decoder.vhd
@@ -11,7 +11,7 @@ use ieee.std_logic_unsigned.all;
use work.nono_const.all;
entity decoder is
- generic(adr : T_ADDRESS);
+ generic(adr : T_ADDRESS:="0000000000");
port(
bus_address : in T_ADDRESS;
cs: out std_logic:='0'
@@ -22,14 +22,13 @@ architecture rtl of decoder is
begin
process(bus_address)
begin
- --if(bus_address = adr)
- --then
+ if(bus_address = adr)
+ then
+ cs<='0';
+ else
cs<='1';
- --else
- -- cs<='0';
- --end if;
+ end if;
end process;
end rtl;
-
diff --git a/2004/n/fpga/src/portserie/fifo.vhd b/2004/n/fpga/src/portserie/fifo.vhd
index 925dbf0..f2a7d22 100644
--- a/2004/n/fpga/src/portserie/fifo.vhd
+++ b/2004/n/fpga/src/portserie/fifo.vhd
@@ -34,7 +34,8 @@ component fifodriver is
);
end component;
-component fifoctlr_cc is
+--component fifoctlr_cc is
+component fifobehav is
port (clock_in: IN std_logic;
read_enable_in: IN std_logic;
write_enable_in: IN std_logic;
@@ -69,7 +70,8 @@ begin
-FIFO1:fifoctlr_cc
+--FIFO1:fifoctlr_cc
+FIFO1:fifobehav
port map(
clock_in=>clock_fifo,
read_enable_in=>read_enable,
@@ -101,3 +103,4 @@ end rtl;
+
diff --git a/2004/n/fpga/src/portserie/fifodriver.vhd b/2004/n/fpga/src/portserie/fifodriver.vhd
index 974871e..15ab56c 100644
--- a/2004/n/fpga/src/portserie/fifodriver.vhd
+++ b/2004/n/fpga/src/portserie/fifodriver.vhd
@@ -18,7 +18,7 @@ entity fifodriver is
fiforead:out std_logic;
fifowrite:out std_logic
);
- constant PRESCAL :integer:= 16;
+ constant PRESCAL :integer:= 1;
end fifodriver;
architecture rtl of fifodriver is
@@ -76,3 +76,4 @@ begin
end rtl;
+
diff --git a/2004/n/fpga/src/portserie/portserie.sws b/2004/n/fpga/src/portserie/portserie.sws
index 6ec0881..e528e6d 100644
--- a/2004/n/fpga/src/portserie/portserie.sws
+++ b/2004/n/fpga/src/portserie/portserie.sws
@@ -149,6 +149,11 @@
[]
[]
[file]
+ name = fifo/fifobehav.vhd
+ [options]
+ []
+ []
+ [file]
name = fifo.vhd
[options]
[]
diff --git a/2004/n/fpga/src/portserie/txserie.vhd b/2004/n/fpga/src/portserie/txserie.vhd
index 81b5b5c..48872cd 100644
--- a/2004/n/fpga/src/portserie/txserie.vhd
+++ b/2004/n/fpga/src/portserie/txserie.vhd
@@ -112,22 +112,20 @@ component decoder
end component;
---signal fifoEmpty: std_logic;
---signal fifoFull: std_logic;
+signal fifoEmpty: std_logic;
+signal fifoFull: std_logic;
--signal fifoLI1: std_logic;
--signal fifoLI0: std_logic;
--signal BdR1: std_logic;
--signal BdR0: std_logic;
signal purge: std_logic:='0';
-signal geneck: std_logic;
signal txck: std_logic;
-signal busck: std_logic;
signal confreg: T_DATA;
signal flagreg: T_DATA;
signal interflag: std_logic_vector(5 downto 0);
signal datareg: T_DATA;
signal inter_data: T_DATA;
-signal txempty: std_logic;
+signal txempty: std_logic:='1';
signal csFifo: std_logic;
signal fifockin: std_logic;
signal fifockout: std_logic;
@@ -146,10 +144,10 @@ FIFO1: fifo
flagreg(5 downto 0)<=interflag;
-fifockin<=csFifo and not rw and busck;
-fifockout<=txempty; -- ŕ vérifier !!! Cette ligne est valable pour
- -- txempty=1 quand le tx est vide
-
+fifockin<=csFifo and clk and not rw;
+fifockout<=txempty and not fifoempty
+; -- ŕ vérifier !!! Cette ligne est valable pour txempty=1 quand le tx est vide
+
TX1 : transmitter
port map(
data_in=>inter_data,
@@ -160,7 +158,7 @@ TX1 : transmitter
CLOCK1 : clockgene
port map(
- ckin=>geneck,
+ ckin=>masterck,
ckout=>txck,
param=>"11" --confreg(1 downto 0)
);
@@ -168,9 +166,12 @@ CLOCK1 : clockgene
--geneck<='1'; --confreg(4) and masterck; -- On/Off et masterck
+fifofull<=interflag(4);
+fifoEmpty<=interflag(5);
+
-- Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0)
RCONF : regIO
- generic map(adr=>A_DATA)
+ generic map(adr=>A_CONFIG)
port map(
bus_address=>bus_address,
bus_data=>bus_data,
@@ -178,7 +179,7 @@ RCONF : regIO
output=>confreg,
rw=>rw,
load=>'0',
- ck=>busck,
+ ck=>clk,
rst=>'0'
);
@@ -192,7 +193,7 @@ RFLAG : regIO
output=>open,
rw=>rw,
load=>'1',
- ck=>busck,
+ ck=>clk,
rst=>'0'
);
@@ -211,3 +212,5 @@ end rtl;
+
+