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Diffstat (limited to '2004/n/fpga/src/portserie/txserie.vhd')
-rw-r--r--2004/n/fpga/src/portserie/txserie.vhd29
1 files changed, 16 insertions, 13 deletions
diff --git a/2004/n/fpga/src/portserie/txserie.vhd b/2004/n/fpga/src/portserie/txserie.vhd
index 81b5b5c..48872cd 100644
--- a/2004/n/fpga/src/portserie/txserie.vhd
+++ b/2004/n/fpga/src/portserie/txserie.vhd
@@ -112,22 +112,20 @@ component decoder
end component;
---signal fifoEmpty: std_logic;
---signal fifoFull: std_logic;
+signal fifoEmpty: std_logic;
+signal fifoFull: std_logic;
--signal fifoLI1: std_logic;
--signal fifoLI0: std_logic;
--signal BdR1: std_logic;
--signal BdR0: std_logic;
signal purge: std_logic:='0';
-signal geneck: std_logic;
signal txck: std_logic;
-signal busck: std_logic;
signal confreg: T_DATA;
signal flagreg: T_DATA;
signal interflag: std_logic_vector(5 downto 0);
signal datareg: T_DATA;
signal inter_data: T_DATA;
-signal txempty: std_logic;
+signal txempty: std_logic:='1';
signal csFifo: std_logic;
signal fifockin: std_logic;
signal fifockout: std_logic;
@@ -146,10 +144,10 @@ FIFO1: fifo
flagreg(5 downto 0)<=interflag;
-fifockin<=csFifo and not rw and busck;
-fifockout<=txempty; -- ŕ vérifier !!! Cette ligne est valable pour
- -- txempty=1 quand le tx est vide
-
+fifockin<=csFifo and clk and not rw;
+fifockout<=txempty and not fifoempty
+; -- ŕ vérifier !!! Cette ligne est valable pour txempty=1 quand le tx est vide
+
TX1 : transmitter
port map(
data_in=>inter_data,
@@ -160,7 +158,7 @@ TX1 : transmitter
CLOCK1 : clockgene
port map(
- ckin=>geneck,
+ ckin=>masterck,
ckout=>txck,
param=>"11" --confreg(1 downto 0)
);
@@ -168,9 +166,12 @@ CLOCK1 : clockgene
--geneck<='1'; --confreg(4) and masterck; -- On/Off et masterck
+fifofull<=interflag(4);
+fifoEmpty<=interflag(5);
+
-- Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0)
RCONF : regIO
- generic map(adr=>A_DATA)
+ generic map(adr=>A_CONFIG)
port map(
bus_address=>bus_address,
bus_data=>bus_data,
@@ -178,7 +179,7 @@ RCONF : regIO
output=>confreg,
rw=>rw,
load=>'0',
- ck=>busck,
+ ck=>clk,
rst=>'0'
);
@@ -192,7 +193,7 @@ RFLAG : regIO
output=>open,
rw=>rw,
load=>'1',
- ck=>busck,
+ ck=>clk,
rst=>'0'
);
@@ -211,3 +212,5 @@ end rtl;
+
+