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authorprot2004-04-03 18:18:36 +0000
committerprot2004-04-03 18:18:36 +0000
commit2a8c2d3c2521de1599f6dc0d5a6b116d9c28bea3 (patch)
treea01bb0350004cc8f0b11cc61b31bde2680051be3 /2004/n/fpga/src/portserie/rxserie
parent9af180b06c093eda9f73bc7e15626cf5ae7ef623 (diff)
Modif aprs cration du top fpga.vhd
Diffstat (limited to '2004/n/fpga/src/portserie/rxserie')
-rw-r--r--2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd24
-rw-r--r--2004/n/fpga/src/portserie/rxserie/rxserie.npl14
-rw-r--r--2004/n/fpga/src/portserie/rxserie/rxserie.vhd13
-rw-r--r--2004/n/fpga/src/portserie/rxserie/sfifo.xco9
4 files changed, 37 insertions, 23 deletions
diff --git a/2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd b/2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd
index ec71a5c..b575b9d 100644
--- a/2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd
+++ b/2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd
@@ -20,14 +20,15 @@ use work.isa_const.all;
rw : in std_logic; -- read (0) / write (1)
bus_data : inout T_DATA;
clk: in std_logic;
+ clk_ref: in std_logic;
rxin: in std_logic;
irqFIFO: out std_logic;
irqRX: out std_logic;
+ irqERR: out std_logic;
csData : in std_logic;
csConfig : in std_logic;
csFlag : in std_logic);
END COMPONENT;
-
signal rst: std_logic;
@@ -36,9 +37,11 @@ signal rw: std_logic;
signal bus_data: T_DATA;
signal data_received: T_DATA;
signal clk: std_logic:='0';
+signal clk_ref: std_logic:='0';
signal rxin: std_logic:='1';
signal irqFIFO: std_logic;
signal irqRX: std_logic;
+signal irqERR: std_logic;
signal csData: std_logic;
signal csConfig: std_logic;
signal csFlag: std_logic;
@@ -47,34 +50,35 @@ signal csFlag: std_logic;
BEGIN
- Inst_rxserie: rxserie PORT MAP(
+ uut: rxserie PORT MAP(
rst => rst,
bus_clk => bus_clk,
rw => rw,
bus_data => bus_data,
clk => clk,
+ clk_ref => clk_ref,
rxin => rxin,
irqFIFO => irqFIFO,
irqRX => irqRX,
+ irqERR => irqERR,
csData => csData,
csConfig => csConfig,
csFlag => csFlag
);
--- baudrate/(16*2) used to generate half clock cycle;
+-- master clock
clk <= (Not clk) after (CK_PERIOD/2);
-- Reset Uart
rst <= '1','0' after (10*CK_PERIOD);
--- feeding back output from transmitter to the input of receiver
-rxin <= not rxin after 12 us;
+-- baudrate/(16*2) used to generate half clock cycle;
+clk_ref <= (not clk_ref) after 135 ns; --1,8432MHz
+-- feeding back output from transmitter to the input of receiver
+rxin <= not rxin after 15751 ns;
--- csData => csData,
--- csConfig => csConfig,
--- csFlag => csFlag
check:process
@@ -124,12 +128,12 @@ begin
csData<='1';
read_bus;
- WAIT FOR 10 us;
+ WAIT FOR 100 us;
csFlag<='1';
read_bus;
- WAIT FOR 10 us;
+ WAIT FOR 100 us;
end process;
END;
diff --git a/2004/n/fpga/src/portserie/rxserie/rxserie.npl b/2004/n/fpga/src/portserie/rxserie/rxserie.npl
index 597ac7c..a400a08 100644
--- a/2004/n/fpga/src/portserie/rxserie/rxserie.npl
+++ b/2004/n/fpga/src/portserie/rxserie/rxserie.npl
@@ -29,10 +29,20 @@ SOURCE sfifo.xco
STIMULUS bch_rxserie.vhd
SOURCE ..\..\modele\nono_const.vhd
SOURCE ..\..\modele\isa_const.vhd
+STIMULUS ..\..\registre\test_reg.vhd
[Normal]
+p_CompxlibOutputDir=xstvhd, spartan2, Design.t_compLibraries, 1079483024, D:\xilinx\vhdl\src
p_CompxlibTargetSimulator=xstvhd, spartan2, Design.t_compLibraries, 1079088462, ModelSim SE
+p_ModelSimListWin=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079738242, False
+p_ModelSimProcWin=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079738242, False
+p_ModelSimSimRunTime_tb=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1080007098, 1000us
+p_ModelSimSourceWin=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079738242, False
+p_ModelSimUutInstName_postPar=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostPlace&RouteVhdlModel, 1079653969, UUT
+p_ModelSimVarsWin=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079738242, False
+_VhdlSimDo_post=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079736489, True
[STATUS-ALL]
-rxserie.ngcFile=WARNINGS,1079226990
-rxserie.ngdFile=WARNINGS,1079300826
+rxserie.ngcFile=WARNINGS,1080007519
+rxserie.ngdFile=WARNINGS,1080007524
+rxserie.postMapVHDLSimModel=WARNINGS,1080007527
[STRATEGY-LIST]
Normal=True
diff --git a/2004/n/fpga/src/portserie/rxserie/rxserie.vhd b/2004/n/fpga/src/portserie/rxserie/rxserie.vhd
index 1ee58ec..e0ec325 100644
--- a/2004/n/fpga/src/portserie/rxserie/rxserie.vhd
+++ b/2004/n/fpga/src/portserie/rxserie/rxserie.vhd
@@ -46,6 +46,7 @@ entity rxserie is
rw : in std_logic; -- read (0) / write (1)
bus_data : inout T_DATA;
clk: in std_logic;
+ clk_ref: in std_logic;
rxin: in std_logic;
irqFIFO: out std_logic;
irqRX: out std_logic;
@@ -110,7 +111,7 @@ end component;
-- signaux
signal rxready:std_logic; -- Receiver data ready to read
-signal rxread:std_logic;
+signal rxread:std_logic:='0';
signal rxparERR:std_logic:='0'; -- Receiver parity error flag
signal rxfrmERR:std_logic:='0'; -- Receiver framing error flag
signal rxovrrERR:std_logic:='0'; -- Receiver overrun error flag
@@ -195,7 +196,7 @@ port map(
-- config
-geneck <= (confreg(4) and clk); -- On/Off et masterck --confreg(4)
+geneck <= (confreg(4) and clk_ref); -- On/Off et clk_ref --confreg(4)
fifopurge<=rst;
-- flags
@@ -208,7 +209,7 @@ flagreg(6) <= rxovrrERR; -- Receiver overrun error flag
-- controle des flux
-fifockout <= (csData and bus_clk and rw and (not rst));
+fifockout <= '1' when (csData='1' and rw='1' and rst='0') else '0';
fifockin <= ((not rxread) and (not fifoFull));
inter_bus <= inter_fifo when (fifockout='1') else (others => 'Z');
@@ -216,9 +217,9 @@ inter_bus <= inter_fifo when (fifockout='1') else (others => 'Z');
bus_data <= inter_bus;
-- irq
-irqFifo <= (fifoLevel(1) and fifoLevel(0)) and confreg(2); --fifo almost full AND Int/En
-irqRx <= (not fifoEmpty) and confreg(3);
-irqErr <= (rxparERR or rxovrrERR or rxfrmERR or fifoFull) and confreg(5);
+irqFifo <= (fifoLevel(1) and fifoLevel(0));-- and confreg(2); --fifo almost full AND Int/En
+irqRx <= (not fifoEmpty);-- and confreg(3);
+irqErr <= (rxparERR or rxovrrERR or rxfrmERR or fifoFull);-- and confreg(5);
-- sortie de donnée du récepteur
process(rxck)
diff --git a/2004/n/fpga/src/portserie/rxserie/sfifo.xco b/2004/n/fpga/src/portserie/rxserie/sfifo.xco
index afcd6a7..61a5042 100644
--- a/2004/n/fpga/src/portserie/rxserie/sfifo.xco
+++ b/2004/n/fpga/src/portserie/rxserie/sfifo.xco
@@ -25,18 +25,17 @@ SET FormalVerification = None
SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim
SELECT Synchronous_FIFO Spartan2 Xilinx,_Inc. 4.0
CSET data_width = 8
-CSET read_error_sense = active_high
+CSET read_error_sense = Active_Low
CSET read_error_flag = true
CSET write_acknowledge_flag = true
CSET write_error_flag = true
CSET data_count = true
CSET memory_type = Distributed_Memory
-CSET read_acknowledge_sense = active_high
+CSET read_acknowledge_sense = Active_Low
CSET component_name = sfifo
CSET fifo_depth = 16
CSET read_acknowledge_flag = true
CSET data_count_width = 2
-CSET write_error_sense = active_high
-CSET write_acknowledge_sense = active_high
+CSET write_error_sense = Active_Low
+CSET write_acknowledge_sense = Active_Low
GENERATE
-