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path: root/2004/n/fpga/src/portserie/rxserie/rxserie.npl
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JDF G
// Created by Project Navigator ver 1.0
PROJECT rxserie
DESIGN rxserie
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s200
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE rxserie.vhd
SOURCE ..\uart\rxcver.vhd
STIMULUS ..\fifo\bch_sfifo.vhd
SOURCE ..\fifo\fifodriver.vhd
STIMULUS ..\fifo\bch_fifodriver.vhd
SOURCE ..\clockgene\clockgene.vhd
SOURCE ..\..\registre\registre.vhd
SOURCE sfifo.xco
STIMULUS bch_rxserie.vhd
SOURCE ..\..\modele\nono_const.vhd
SOURCE ..\..\modele\isa_const.vhd
STIMULUS ..\..\registre\test_reg.vhd
[Normal]
p_CompxlibOutputDir=xstvhd, spartan2, Design.t_compLibraries, 1079483024, D:\xilinx\vhdl\src
p_CompxlibTargetSimulator=xstvhd, spartan2, Design.t_compLibraries, 1079088462, ModelSim SE
p_ModelSimListWin=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079738242, False
p_ModelSimProcWin=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079738242, False
p_ModelSimSimRunTime_tb=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1080007098, 1000us
p_ModelSimSourceWin=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079738242, False
p_ModelSimUutInstName_postPar=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostPlace&RouteVhdlModel, 1079653969, UUT
p_ModelSimVarsWin=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079738242, False
_VhdlSimDo_post=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079736489, True
[STATUS-ALL]
rxserie.ngcFile=WARNINGS,1080007519
rxserie.ngdFile=WARNINGS,1080007524
rxserie.postMapVHDLSimModel=WARNINGS,1080007527
[STRATEGY-LIST]
Normal=True