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authorprot2004-03-14 23:59:28 +0000
committerprot2004-03-14 23:59:28 +0000
commit996c7b9bc5863e839f7352ee7fe3ca0be8dca944 (patch)
treeb7c5425251e9abc25d5ae6d5ec0ab9a35e729759 /2004/n/fpga/src/portserie/fifo/bch_fifodriver.vhd
parent503437bcc6c78c18a1ffe53c8ce30d6b637e2423 (diff)
Les différentes fifos
Diffstat (limited to '2004/n/fpga/src/portserie/fifo/bch_fifodriver.vhd')
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diff --git a/2004/n/fpga/src/portserie/fifo/bch_fifodriver.vhd b/2004/n/fpga/src/portserie/fifo/bch_fifodriver.vhd
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+-- TestBench Template
+
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.ALL;
+ USE ieee.numeric_std.ALL;
+
+ ENTITY bch_fd IS
+ END bch_fd;
+
+ ARCHITECTURE behavior OF bch_fd IS
+
+ -- Component Declaration
+ COMPONENT fifodriver
+ PORT(
+ clk: in std_logic;
+ rst: in std_logic;
+ readreq: in std_logic;
+ writereq: in std_logic;
+ din: IN std_logic_VECTOR(7 downto 0);
+ dout: OUT std_logic_VECTOR(7 downto 0);
+ dready: out std_logic;
+ full: OUT std_logic;
+ empty: OUT std_logic;
+ data_count: OUT std_logic_VECTOR(1 downto 0)
+ );
+ END COMPONENT;
+
+signal clk:std_logic:='0';
+signal rst:std_logic;
+signal readreq:std_logic:='0';
+signal writereq:std_logic:='0';
+signal din: std_logic_VECTOR(7 downto 0):="01010101";
+signal dout: std_logic_VECTOR(7 downto 0);
+signal dready: std_logic;
+signal full: std_logic;
+signal empty: std_logic;
+signal data_count: std_logic_VECTOR(1 downto 0);
+
+
+
+
+ BEGIN
+
+Inst_fifodriver: fifodriver PORT MAP(
+ clk => clk,
+ rst => rst,
+ readreq => readreq,
+ writereq => writereq,
+ din => din,
+ dout => dout,
+ dready => dready,
+ full => full,
+ empty => empty,
+ data_count => data_count
+ );
+
+
+ din <= std_logic_vector(unsigned(din) + 1) after 8 ns;
+ rst<='1' , '0' after 10 ns;
+ clk <= not clk after 1 ns;
+ writereq <= not writereq after 13 ns;
+ readreq <= not readreq after 17 ns;
+
+
+
+
+ END;