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authorprot2004-03-14 23:59:28 +0000
committerprot2004-03-14 23:59:28 +0000
commit996c7b9bc5863e839f7352ee7fe3ca0be8dca944 (patch)
treeb7c5425251e9abc25d5ae6d5ec0ab9a35e729759 /2004/n/fpga/src
parent503437bcc6c78c18a1ffe53c8ce30d6b637e2423 (diff)
Les différentes fifos
Diffstat (limited to '2004/n/fpga/src')
-rw-r--r--2004/n/fpga/src/portserie/fifo/bch_afifo.vhd83
-rw-r--r--2004/n/fpga/src/portserie/fifo/bch_fifodriver.vhd67
-rw-r--r--2004/n/fpga/src/portserie/fifo/bch_sfifo.vhd70
-rw-r--r--2004/n/fpga/src/portserie/fifo/fifo.npl32
-rw-r--r--2004/n/fpga/src/portserie/fifo/fifodriver.vhd130
-rw-r--r--2004/n/fpga/src/portserie/fifo/sfifo.xco42
6 files changed, 424 insertions, 0 deletions
diff --git a/2004/n/fpga/src/portserie/fifo/bch_afifo.vhd b/2004/n/fpga/src/portserie/fifo/bch_afifo.vhd
new file mode 100644
index 0000000..b593c77
--- /dev/null
+++ b/2004/n/fpga/src/portserie/fifo/bch_afifo.vhd
@@ -0,0 +1,83 @@
+-- TestBench Template
+
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.ALL;
+ USE ieee.numeric_std.ALL;
+
+ ENTITY testbench IS
+ END testbench;
+
+ ARCHITECTURE behavior OF testbench IS
+
+ -- Component Declaration
+component afifo
+ port (
+ din: IN std_logic_VECTOR(7 downto 0);
+ wr_en: IN std_logic;
+ wr_clk: IN std_logic;
+ rd_en: IN std_logic;
+ rd_clk: IN std_logic;
+ ainit: IN std_logic;
+ dout: OUT std_logic_VECTOR(7 downto 0);
+ full: OUT std_logic;
+ empty: OUT std_logic;
+ almost_full: OUT std_logic;
+ almost_empty: OUT std_logic;
+ wr_count: OUT std_logic_VECTOR(1 downto 0);
+ rd_count: OUT std_logic_VECTOR(1 downto 0);
+ rd_ack: OUT std_logic;
+ rd_err: OUT std_logic;
+ wr_ack: OUT std_logic;
+ wr_err: OUT std_logic);
+end component;
+
+signal din: std_logic_VECTOR(7 downto 0):="01010101";
+signal wr_en: std_logic:='1';
+signal wr_clk: std_logic:='0';
+signal rd_en: std_logic:='1';
+signal rd_clk: std_logic:='0';
+signal ainit: std_logic:='1';
+signal dout: std_logic_VECTOR(7 downto 0);
+signal full: std_logic;
+signal empty: std_logic;
+signal almost_full: std_logic;
+signal almost_empty: std_logic;
+signal wr_count: std_logic_VECTOR(1 downto 0);
+signal rd_count: std_logic_VECTOR(1 downto 0);
+signal rd_ack: std_logic;
+signal rd_err: std_logic;
+signal wr_ack: std_logic;
+signal wr_err: std_logic;
+
+ BEGIN
+
+
+ -- Component Instantiation
+U0 : afifo
+ port map (
+ din => din,
+ wr_en => wr_en,
+ wr_clk => wr_clk,
+ rd_en => rd_en,
+ rd_clk => rd_clk,
+ ainit => ainit,
+ dout => dout,
+ full => full,
+ empty => empty,
+ almost_full => almost_full,
+ almost_empty => almost_empty,
+ wr_count => wr_count,
+ rd_count => rd_count,
+ rd_ack => rd_ack,
+ rd_err => rd_err,
+ wr_ack => wr_ack,
+ wr_err => wr_err);
+
+
+ din <= std_logic_vector(unsigned(din) + 1) after 5 ns;
+ ainit <= '1' , '0' after 10 ns;
+ rd_clk <= not rd_clk after 2 ns;
+ wr_clk <= not wr_clk after 3 ns;
+ rd_en <= '0' , '1' after 50 ns;
+
+ END;
diff --git a/2004/n/fpga/src/portserie/fifo/bch_fifodriver.vhd b/2004/n/fpga/src/portserie/fifo/bch_fifodriver.vhd
new file mode 100644
index 0000000..a109693
--- /dev/null
+++ b/2004/n/fpga/src/portserie/fifo/bch_fifodriver.vhd
@@ -0,0 +1,67 @@
+-- TestBench Template
+
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.ALL;
+ USE ieee.numeric_std.ALL;
+
+ ENTITY bch_fd IS
+ END bch_fd;
+
+ ARCHITECTURE behavior OF bch_fd IS
+
+ -- Component Declaration
+ COMPONENT fifodriver
+ PORT(
+ clk: in std_logic;
+ rst: in std_logic;
+ readreq: in std_logic;
+ writereq: in std_logic;
+ din: IN std_logic_VECTOR(7 downto 0);
+ dout: OUT std_logic_VECTOR(7 downto 0);
+ dready: out std_logic;
+ full: OUT std_logic;
+ empty: OUT std_logic;
+ data_count: OUT std_logic_VECTOR(1 downto 0)
+ );
+ END COMPONENT;
+
+signal clk:std_logic:='0';
+signal rst:std_logic;
+signal readreq:std_logic:='0';
+signal writereq:std_logic:='0';
+signal din: std_logic_VECTOR(7 downto 0):="01010101";
+signal dout: std_logic_VECTOR(7 downto 0);
+signal dready: std_logic;
+signal full: std_logic;
+signal empty: std_logic;
+signal data_count: std_logic_VECTOR(1 downto 0);
+
+
+
+
+ BEGIN
+
+Inst_fifodriver: fifodriver PORT MAP(
+ clk => clk,
+ rst => rst,
+ readreq => readreq,
+ writereq => writereq,
+ din => din,
+ dout => dout,
+ dready => dready,
+ full => full,
+ empty => empty,
+ data_count => data_count
+ );
+
+
+ din <= std_logic_vector(unsigned(din) + 1) after 8 ns;
+ rst<='1' , '0' after 10 ns;
+ clk <= not clk after 1 ns;
+ writereq <= not writereq after 13 ns;
+ readreq <= not readreq after 17 ns;
+
+
+
+
+ END;
diff --git a/2004/n/fpga/src/portserie/fifo/bch_sfifo.vhd b/2004/n/fpga/src/portserie/fifo/bch_sfifo.vhd
new file mode 100644
index 0000000..a3d930d
--- /dev/null
+++ b/2004/n/fpga/src/portserie/fifo/bch_sfifo.vhd
@@ -0,0 +1,70 @@
+-- TestBench Template
+
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.ALL;
+ USE ieee.numeric_std.ALL;
+
+ ENTITY bch_sfifo IS
+ END bch_sfifo;
+
+ ARCHITECTURE behavior OF bch_sfifo IS
+ -- Component Declaration
+component sfifo
+ port (
+ clk: IN std_logic;
+ sinit: IN std_logic;
+ din: IN std_logic_VECTOR(7 downto 0);
+ wr_en: IN std_logic;
+ rd_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(7 downto 0);
+ full: OUT std_logic;
+ empty: OUT std_logic;
+ rd_ack: OUT std_logic;
+ wr_ack: OUT std_logic;
+ rd_err: OUT std_logic;
+ wr_err: OUT std_logic;
+ data_count: OUT std_logic_VECTOR(1 downto 0));
+end component;
+
+signal din: std_logic_VECTOR(7 downto 0):="01010101";
+signal wr_en: std_logic:='1';
+signal clk: std_logic:='0';
+signal rd_en: std_logic:='1';
+signal sinit: std_logic:='1';
+signal dout: std_logic_VECTOR(7 downto 0);
+signal full: std_logic;
+signal empty: std_logic;
+signal data_count: std_logic_VECTOR(1 downto 0);
+signal rd_ack: std_logic;
+signal rd_err: std_logic;
+signal wr_ack: std_logic;
+signal wr_err: std_logic;
+
+ BEGIN
+
+
+ -- Component Instantiation
+U0 : sfifo
+ port map (
+ clk => clk,
+ sinit => sinit,
+ din => din,
+ wr_en => wr_en,
+ rd_en => rd_en,
+ dout => dout,
+ full => full,
+ empty => empty,
+ rd_ack => rd_ack,
+ wr_ack => wr_ack,
+ rd_err => rd_err,
+ wr_err => wr_err,
+ data_count => data_count);
+
+
+
+ din <= std_logic_vector(unsigned(din) + 1) after 8 ns;
+ sinit <= '1' , '0' after 10 ns;
+ clk <= not clk after 3 ns;
+ rd_en <= '0' , '1' after 50 ns;
+
+ END;
diff --git a/2004/n/fpga/src/portserie/fifo/fifo.npl b/2004/n/fpga/src/portserie/fifo/fifo.npl
new file mode 100644
index 0000000..c8ba229
--- /dev/null
+++ b/2004/n/fpga/src/portserie/fifo/fifo.npl
@@ -0,0 +1,32 @@
+JDF G
+// Created by Project Navigator ver 1.0
+PROJECT fifo
+DESIGN fifo
+DEVFAM spartan2
+DEVFAMTIME 0
+DEVICE xc2s200
+DEVICETIME 0
+DEVPKG pq208
+DEVPKGTIME 0
+DEVSPEED -6
+DEVSPEEDTIME 0
+DEVTOPLEVELMODULETYPE HDL
+TOPLEVELMODULETYPETIME 0
+DEVSYNTHESISTOOL XST (VHDL/Verilog)
+SYNTHESISTOOLTIME 0
+DEVSIMULATOR Modelsim
+SIMULATORTIME 0
+DEVGENERATEDSIMULATIONMODEL VHDL
+GENERATEDSIMULATIONMODELTIME 0
+STIMULUS bch_afifo.vhd
+SOURCE fifodriver.vhd
+STIMULUS bch_fifodriver.vhd
+SOURCE ..\..\modele\nono_const.vhd
+SOURCE sfifo.xco
+STIMULUS bch_sfifo.vhd
+[Normal]
+p_CompxlibTargetSimulator=xstvhd, spartan2, Design.t_compLibraries, 1078952453, ModelSim SE
+[STATUS-ALL]
+bch_fifodriver.vhd.testbenchRpt=ERRORS,0
+[STRATEGY-LIST]
+Normal=True
diff --git a/2004/n/fpga/src/portserie/fifo/fifodriver.vhd b/2004/n/fpga/src/portserie/fifo/fifodriver.vhd
new file mode 100644
index 0000000..3830e93
--- /dev/null
+++ b/2004/n/fpga/src/portserie/fifo/fifodriver.vhd
@@ -0,0 +1,130 @@
+-- fifodriver.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre Prot
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.nono_const.all;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+-- pilote de fifo
+entity fifodriver is
+ port(
+ clk: in std_logic;
+ rst: in std_logic;
+ readreq: in std_logic;
+ writereq: in std_logic;
+ din: IN std_logic_VECTOR(7 downto 0);
+ dout: OUT std_logic_VECTOR(7 downto 0);
+ dready: out std_logic;
+ full: OUT std_logic;
+ empty: OUT std_logic;
+ data_count: OUT std_logic_VECTOR(1 downto 0)
+ );
+end fifodriver;
+
+-- arch
+architecture rtl of fifodriver is
+component sfifo
+ port (
+ clk: IN std_logic;
+ sinit: IN std_logic;
+ din: IN std_logic_VECTOR(7 downto 0);
+ wr_en: IN std_logic;
+ rd_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(7 downto 0);
+ full: OUT std_logic;
+ empty: OUT std_logic;
+ rd_ack: OUT std_logic;
+ wr_ack: OUT std_logic;
+ rd_err: OUT std_logic;
+ wr_err: OUT std_logic;
+ data_count: OUT std_logic_VECTOR(1 downto 0));
+end component;
+
+
+
+signal wr_en:std_logic;
+signal rd_en:std_logic;
+signal state_read:integer:=0;
+signal state_write:integer:=0;
+
+signal rd_ack:std_logic;
+signal wr_ack:std_logic;
+signal rd_err:std_logic;
+signal wr_err:std_logic;
+
+
+begin
+ -- Component Instantiation
+U0 : sfifo
+ port map (
+ clk => clk,
+ sinit => rst,
+ din => din,
+ wr_en => wr_en,
+ rd_en => rd_en,
+ dout => dout,
+ full => full,
+ empty => empty,
+ rd_ack => rd_ack,
+ wr_ack => wr_ack,
+ rd_err => rd_err,
+ wr_err => wr_err,
+ data_count => data_count);
+
+
+ -- process
+ read:process(clk)
+ begin
+ if(rst='1') then
+ rd_en<='0';
+ elsif(clk'event and clk='0') then
+ rd_en<='0';
+ dready<='0';
+ case state_read is
+ when 0 => if(readreq='1') then
+ state_read<=1;
+ rd_en<='1';
+ end if;
+ when 1 => state_read<=2;
+ dready<='1';
+ when 2 => if(readreq='0') then
+ state_read<=0;
+ else
+ state_read<=3;
+ end if;
+ when 3 => if(readreq='0') then
+ state_read<=0;
+ end if;
+ when others => null;
+ end case;
+ end if;
+ end process;
+
+ write:process(clk)
+ begin
+ if(rst='1') then
+ wr_en<='0';
+ elsif(clk'event and clk='0') then
+ wr_en<='0';
+ case state_write is
+ when 0 => if(writereq='1') then
+ state_write<=1;
+ wr_en<='1';
+ end if;
+ when 1 => state_write<=2;
+ when 2 => if(writereq='0') then
+ state_write<=0;
+ end if;
+ when others => null;
+ end case;
+ end if;
+ end process;
+
+end rtl;
+
diff --git a/2004/n/fpga/src/portserie/fifo/sfifo.xco b/2004/n/fpga/src/portserie/fifo/sfifo.xco
new file mode 100644
index 0000000..306f531
--- /dev/null
+++ b/2004/n/fpga/src/portserie/fifo/sfifo.xco
@@ -0,0 +1,42 @@
+# Xilinx CORE Generator 6.1.03i
+# Username = Administrateur
+# COREGenPath = D:\xilinx\coregen
+# ProjectPath = D:\vhdl\robot\carte_fpga\src\portserie\fifo
+# ExpandedProjectPath = D:\vhdl\robot\carte_fpga\src\portserie\fifo
+# OverwriteFiles = true
+# Core name: sfifo
+# Number of Primitives in design: 120
+# Number of CLBs used in design cannot be determined when there is no RPMed logic
+# Number of Slices used in design cannot be determined when there is no RPMed logic
+# Number of LUT sites used in design: 70
+# Number of LUTs used in design: 46
+# Number of REG used in design: 24
+# Number of SRL16s used in design: 24
+# Number of Distributed RAM primitives used in design: 0
+# Number of Block Memories used in design: 0
+# Number of Dedicated Multipliers used in design: 0
+# Number of HU_SETs used: 0
+#
+SET BusFormat = BusFormatAngleBracketNotRipped
+SET XilinxFamily = Spartan2
+SET OutputOption = OutputProducts
+SET FlowVendor = Foundation_iSE
+SET FormalVerification = None
+SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim
+SELECT Synchronous_FIFO Spartan2 Xilinx,_Inc. 4.0
+CSET data_width = 8
+CSET read_error_sense = active_high
+CSET read_error_flag = true
+CSET write_acknowledge_flag = true
+CSET write_error_flag = true
+CSET data_count = true
+CSET memory_type = Distributed_Memory
+CSET read_acknowledge_sense = active_high
+CSET component_name = sfifo
+CSET fifo_depth = 32
+CSET read_acknowledge_flag = true
+CSET data_count_width = 2
+CSET write_error_sense = active_high
+CSET write_acknowledge_sense = active_high
+GENERATE
+