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authorgalmes2004-02-16 15:22:47 +0000
committergalmes2004-02-16 15:22:47 +0000
commit111d703989aacc6f278ca0b67cf7d918aadfd34b (patch)
tree66ae95b4d3e1b1c99824cdd9a78b0093e5c95500 /2004/n/fpga/src/modele/modele.vhd
parent920018a9a8650623da4161d2f37c7ffacdf162a2 (diff)
Ajout d'un modèle pour module. Pas pu le tester ni simuler
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+-- modele.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre-André Galmes
+-- Fichier modèle pour la déclaration de module.
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.nono_const.all
+
+entity modele is
+ generic (
+ -- adresses des différents registres du module.
+ A_REG1 : T_ADDRESS := A_REG_IO_DIRECTION;
+ A_REG2 : T_ADDRESS := A_REG_IO_DATA;
+ A_REG3 : T_ADDRESS := A_REG_IO_INTERRUPT_MASK
+ -- si autre choses à déclarer...
+ );
+ port (
+ rst : in std_logic;
+ clk : in std_logic;
+
+ -- XXX : savoir si read = 0 ou 1 !!
+ rw : in std_logic; -- read (0) / write (1)
+
+ bus_data : inout std_logic_vector ((NB_BIT_DATA - 1) downto 0);
+ bus_address : in std_logic_vector ((NB_BIT_ADDRESS - 1) downto 0)
+ );
+end entity;
+
+architecture test_modele of modele is
+begin
+ process (rst, clk)
+ begin
+ if (rst = '1') then
+ bus_data <= x"00";
+ elsif (ck'event and ck = '1') then
+ if (bus_address = A_REG1) then
+ bus_data <= "01";
+ else
+ if (bus_address = A_REG2) then
+ bus_data <= "02";
+ elsif (bus_address = A_REG2) then
+ bus_data <= "03";
+ end if;
+ end if;
+ end if;
+ end process;
+end test_modele;