From 111d703989aacc6f278ca0b67cf7d918aadfd34b Mon Sep 17 00:00:00 2001 From: galmes Date: Mon, 16 Feb 2004 15:22:47 +0000 Subject: Ajout d'un modèle pour module. Pas pu le tester ni simuler --- 2004/n/fpga/src/modele/modele.vhd | 49 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 2004/n/fpga/src/modele/modele.vhd (limited to '2004/n/fpga/src/modele/modele.vhd') diff --git a/2004/n/fpga/src/modele/modele.vhd b/2004/n/fpga/src/modele/modele.vhd new file mode 100644 index 0000000..701ccbc --- /dev/null +++ b/2004/n/fpga/src/modele/modele.vhd @@ -0,0 +1,49 @@ +-- modele.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre-André Galmes +-- Fichier modèle pour la déclaration de module. + +library ieee; +use ieee.std_logic_1164.all; + +use work.nono_const.all + +entity modele is + generic ( + -- adresses des différents registres du module. + A_REG1 : T_ADDRESS := A_REG_IO_DIRECTION; + A_REG2 : T_ADDRESS := A_REG_IO_DATA; + A_REG3 : T_ADDRESS := A_REG_IO_INTERRUPT_MASK + -- si autre choses à déclarer... + ); + port ( + rst : in std_logic; + clk : in std_logic; + + -- XXX : savoir si read = 0 ou 1 !! + rw : in std_logic; -- read (0) / write (1) + + bus_data : inout std_logic_vector ((NB_BIT_DATA - 1) downto 0); + bus_address : in std_logic_vector ((NB_BIT_ADDRESS - 1) downto 0) + ); +end entity; + +architecture test_modele of modele is +begin + process (rst, clk) + begin + if (rst = '1') then + bus_data <= x"00"; + elsif (ck'event and ck = '1') then + if (bus_address = A_REG1) then + bus_data <= "01"; + else + if (bus_address = A_REG2) then + bus_data <= "02"; + elsif (bus_address = A_REG2) then + bus_data <= "03"; + end if; + end if; + end if; + end process; +end test_modele; -- cgit v1.2.3