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authorchrysn2012-10-18 13:30:19 +0200
committerchrysn2012-10-18 13:31:17 +0200
commit172ce56e3cbc7e64fd3e6a3dc564eb10e0ca766a (patch)
treeb26153bbc41374e35370214a765b87b25bc01c33 /include/libopencm3/stm32
parent7c33025c318bcc43cfcd3a23a76d14b299fecc0a (diff)
parent94ce82396bd69dfde8807dad27e23f30913247aa (diff)
nvic unification
* created include/libopencm3/cm3/nvic.h from the respective stm32 and lpc43xx files. the chip specific definitions were left in place (they were already split out in sthe stm32 case). * created lib/cm3/nvic.c from the respective stm32 and lpc43xx files. a hack from the lpc43xx was taken over (for manipulating the internal interrupts); for now it'll work. * created a include/libopencm3/dispatch/ directory where the dispatching of files with common interfaces but different implenentations can happen; for now, an nvic.h there includes the respective irq name definitions. (future implementations might have some automation or preprocessor magic there; so far, it's manual dispatching based on defines.) * for efm32, an nvic.h gets generated from an interrupt list, the rationale for code generation is, in this case, that this can't be done easily in c preprocessor, and it's really just a list of definitions and not code proper. * examples now include <libopencm3/cm3/nvic.h> instead of <libopencm3/stm32/nvic.h>
Diffstat (limited to 'include/libopencm3/stm32')
-rw-r--r--include/libopencm3/stm32/f1/nvic_f1.h2
-rw-r--r--include/libopencm3/stm32/f2/nvic_f2.h2
-rw-r--r--include/libopencm3/stm32/f4/nvic_f4.h2
-rw-r--r--include/libopencm3/stm32/nvic.h135
4 files changed, 6 insertions, 135 deletions
diff --git a/include/libopencm3/stm32/f1/nvic_f1.h b/include/libopencm3/stm32/f1/nvic_f1.h
index 5223bb6..1544e4f 100644
--- a/include/libopencm3/stm32/f1/nvic_f1.h
+++ b/include/libopencm3/stm32/f1/nvic_f1.h
@@ -109,6 +109,8 @@ LGPL License Terms @ref lgpl_license
#define NVIC_CAN2_RX1_IRQ 65
#define NVIC_CAN2_SCE_IRQ 66
#define NVIC_OTG_FS_IRQ 67
+
+#define NVIC_IRQ_COUNT 68
/**@}*/
#endif
diff --git a/include/libopencm3/stm32/f2/nvic_f2.h b/include/libopencm3/stm32/f2/nvic_f2.h
index 2bf2997..65a990d 100644
--- a/include/libopencm3/stm32/f2/nvic_f2.h
+++ b/include/libopencm3/stm32/f2/nvic_f2.h
@@ -109,4 +109,6 @@
#define NVIC_CRYP_IRQ 79
#define NVIC_HASH_RNG_IRQ 80
+#define NVIC_IRQ_COUNT 81
+
#endif
diff --git a/include/libopencm3/stm32/f4/nvic_f4.h b/include/libopencm3/stm32/f4/nvic_f4.h
index 91b6c25..013e3b5 100644
--- a/include/libopencm3/stm32/f4/nvic_f4.h
+++ b/include/libopencm3/stm32/f4/nvic_f4.h
@@ -109,4 +109,6 @@
#define NVIC_CRYP_IRQ 79
#define NVIC_HASH_RNG_IRQ 80
+#define NVIC_IRQ_COUNT 81
+
#endif
diff --git a/include/libopencm3/stm32/nvic.h b/include/libopencm3/stm32/nvic.h
deleted file mode 100644
index 694fab8..0000000
--- a/include/libopencm3/stm32/nvic.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/** @defgroup STM32F_nvic_defines NVIC Defines
-
-@brief <b>libopencm3 STM32F Nested Vectored Interrupt Controller</b>
-
-@ingroup STM32F_defines
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
-
-@date 18 August 2012
-
-LGPL License Terms @ref lgpl_license
- */
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-/**@{*/
-
-#ifndef LIBOPENCM3_NVIC_H
-#define LIBOPENCM3_NVIC_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- NVIC Registers ------------------------------------------------------ */
-
-/* ISER: Interrupt Set Enable Registers */
-/* Note: 8 32bit Registers */
-#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4))
-
-/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
-
-/* ICER: Interrupt Clear Enable Registers */
-/* Note: 8 32bit Registers */
-#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4))
-
-/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
-
-/* ISPR: Interrupt Set Pending Registers */
-/* Note: 8 32bit Registers */
-#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4))
-
-/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
-
-/* ICPR: Interrupt Clear Pending Registers */
-/* Note: 8 32bit Registers */
-#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4))
-
-/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
-
-/* IABR: Interrupt Active Bit Register */
-/* Note: 8 32bit Registers */
-#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4))
-
-/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
-
-/* IPR: Interrupt Priority Registers */
-/* Note: 240 8bit Registers */
-#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id)
-
-/* STIR: Software Trigger Interrupt Register */
-#define NVIC_STIR MMIO32(STIR_BASE)
-
-/* --- IRQ channel numbers-------------------------------------------------- */
-
-/* Cortex M3 System Interrupts */
-/** @defgroup nvic_sysint Cortex M3 System Interrupts
-@ingroup STM32F_nvic_defines
-
-IRQ numbers -3 and -6 to -9 are reserved
-@{*/
-#define NVIC_NMI_IRQ -14
-#define NVIC_HARD_FAULT_IRQ -13
-#define NVIC_MEM_MANAGE_IRQ -12
-#define NVIC_BUS_FAULT_IRQ -11
-#define NVIC_USAGE_FAULT_IRQ -10
-/* irq numbers -6 to -9 are reserved */
-#define NVIC_SV_CALL_IRQ -5
-#define DEBUG_MONITOR_IRQ -4
-/* irq number -3 reserved */
-#define NVIC_PENDSV_IRQ -2
-#define NVIC_SYSTICK_IRQ -1
-/**@}*/
-
-
-/* Note: User interrupts are family specific and are defined in a family
- * specific header file in the corresponding subfolder.
- */
-
-#if defined(STM32F1)
-# include <libopencm3/stm32/f1/nvic_f1.h>
-#elif defined(STM32F2)
-# include <libopencm3/stm32/f2/nvic_f2.h>
-#elif defined(STM32F4)
-# include <libopencm3/stm32/f4/nvic_f4.h>
-#else
-# error "stm32 family not defined."
-#endif
-
-
-/* --- NVIC functions ------------------------------------------------------ */
-
-BEGIN_DECLS
-
-void nvic_enable_irq(u8 irqn);
-void nvic_disable_irq(u8 irqn);
-u8 nvic_get_pending_irq(u8 irqn);
-void nvic_set_pending_irq(u8 irqn);
-void nvic_clear_pending_irq(u8 irqn);
-u8 nvic_get_active_irq(u8 irqn);
-u8 nvic_get_irq_enabled(u8 irqn);
-void nvic_set_priority(u8 irqn, u8 priority);
-void nvic_generate_software_interrupt(u16 irqn);
-
-END_DECLS
-
-#endif
-/**@}*/
-