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authorchrysn2012-10-18 13:30:19 +0200
committerchrysn2012-10-18 13:31:17 +0200
commit172ce56e3cbc7e64fd3e6a3dc564eb10e0ca766a (patch)
treeb26153bbc41374e35370214a765b87b25bc01c33 /include/libopencm3
parent7c33025c318bcc43cfcd3a23a76d14b299fecc0a (diff)
parent94ce82396bd69dfde8807dad27e23f30913247aa (diff)
nvic unification
* created include/libopencm3/cm3/nvic.h from the respective stm32 and lpc43xx files. the chip specific definitions were left in place (they were already split out in sthe stm32 case). * created lib/cm3/nvic.c from the respective stm32 and lpc43xx files. a hack from the lpc43xx was taken over (for manipulating the internal interrupts); for now it'll work. * created a include/libopencm3/dispatch/ directory where the dispatching of files with common interfaces but different implenentations can happen; for now, an nvic.h there includes the respective irq name definitions. (future implementations might have some automation or preprocessor magic there; so far, it's manual dispatching based on defines.) * for efm32, an nvic.h gets generated from an interrupt list, the rationale for code generation is, in this case, that this can't be done easily in c preprocessor, and it's really just a list of definitions and not code proper. * examples now include <libopencm3/cm3/nvic.h> instead of <libopencm3/stm32/nvic.h>
Diffstat (limited to 'include/libopencm3')
-rw-r--r--include/libopencm3/cm3/nvic.h (renamed from include/libopencm3/stm32/nvic.h)52
-rw-r--r--include/libopencm3/cm3/vector.h5
-rw-r--r--include/libopencm3/dispatch/nvic.h20
-rw-r--r--include/libopencm3/efm32/tinygecko/Makefile2
-rw-r--r--include/libopencm3/efm32/tinygecko/irq.h130
-rw-r--r--include/libopencm3/efm32/tinygecko/irq.yaml28
-rwxr-xr-xinclude/libopencm3/efm32/tinygecko/irq2nvic_h92
-rw-r--r--include/libopencm3/lpc43xx/nvic.h87
-rw-r--r--include/libopencm3/stm32/f1/nvic_f1.h2
-rw-r--r--include/libopencm3/stm32/f2/nvic_f2.h2
-rw-r--r--include/libopencm3/stm32/f4/nvic_f4.h2
11 files changed, 173 insertions, 249 deletions
diff --git a/include/libopencm3/stm32/nvic.h b/include/libopencm3/cm3/nvic.h
index 694fab8..3f83285 100644
--- a/include/libopencm3/stm32/nvic.h
+++ b/include/libopencm3/cm3/nvic.h
@@ -1,21 +1,9 @@
-/** @defgroup STM32F_nvic_defines NVIC Defines
-
-@brief <b>libopencm3 STM32F Nested Vectored Interrupt Controller</b>
-
-@ingroup STM32F_defines
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
-
-@date 18 August 2012
-
-LGPL License Terms @ref lgpl_license
- */
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
+ * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
+ * Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
@@ -30,13 +18,27 @@ LGPL License Terms @ref lgpl_license
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/** @defgroup CM3_nvic_defines NVIC Defines
+
+@brief <b>libopencm3 Cortex Nested Vectored Interrupt Controller</b>
+
+@ingroup CM3_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
/**@{*/
#ifndef LIBOPENCM3_NVIC_H
#define LIBOPENCM3_NVIC_H
-#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
+#include <libopencm3/cm3/memorymap.h>
/* --- NVIC Registers ------------------------------------------------------ */
@@ -79,9 +81,9 @@ LGPL License Terms @ref lgpl_license
/* --- IRQ channel numbers-------------------------------------------------- */
-/* Cortex M3 System Interrupts */
-/** @defgroup nvic_sysint Cortex M3 System Interrupts
-@ingroup STM32F_nvic_defines
+/* Cortex M3 and M4 System Interrupts */
+/** @defgroup nvic_sysint Cortex M3/M4 System Interrupts
+@ingroup CM3_nvic_defines
IRQ numbers -3 and -6 to -9 are reserved
@{*/
@@ -98,21 +100,11 @@ IRQ numbers -3 and -6 to -9 are reserved
#define NVIC_SYSTICK_IRQ -1
/**@}*/
-
/* Note: User interrupts are family specific and are defined in a family
* specific header file in the corresponding subfolder.
*/
-#if defined(STM32F1)
-# include <libopencm3/stm32/f1/nvic_f1.h>
-#elif defined(STM32F2)
-# include <libopencm3/stm32/f2/nvic_f2.h>
-#elif defined(STM32F4)
-# include <libopencm3/stm32/f4/nvic_f4.h>
-#else
-# error "stm32 family not defined."
-#endif
-
+#include <libopencm3/dispatch/nvic.h>
/* --- NVIC functions ------------------------------------------------------ */
@@ -131,5 +123,3 @@ void nvic_generate_software_interrupt(u16 irqn);
END_DECLS
#endif
-/**@}*/
-
diff --git a/include/libopencm3/cm3/vector.h b/include/libopencm3/cm3/vector.h
index 198992b..f78e9d8 100644
--- a/include/libopencm3/cm3/vector.h
+++ b/include/libopencm3/cm3/vector.h
@@ -38,8 +38,7 @@
#define LIBOPENCM3_VECTOR_H
#include <libopencm3/cm3/common.h>
-
-// #include "irq.h" /* we'll nede some definitions */
+#include <libopencm3/cm3/nvic.h>
/** Type of an interrupt function. Only used to avoid hard-to-read function
* pointers in the efm32_vector_table_t struct. */
@@ -59,7 +58,7 @@ typedef struct {
vector_table_entry_t reserved_x0034;
vector_table_entry_t pend_sv;
vector_table_entry_t systick;
- vector_table_entry_t irq[IRQ_COUNT];
+ vector_table_entry_t irq[NVIC_IRQ_COUNT];
} vector_table_t;
#endif
diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h
new file mode 100644
index 0000000..a405b5d
--- /dev/null
+++ b/include/libopencm3/dispatch/nvic.h
@@ -0,0 +1,20 @@
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/nvic_f1.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/nvic_f2.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/nvic_f4.h>
+
+#elif defined(TINYGECKO)
+# include <libopencm3/efm32/tinygecko/nvic.h>
+
+#elif defined(LPC43XX)
+# include <libopencm3/lpc43xx/nvic.h>
+
+#else
+# warning"no chipset defined; user interrupts are disabled"
+
+#define NVIC_IRQ_COUNT 0
+#define IRQ_HANDLERS
+
+#endif
diff --git a/include/libopencm3/efm32/tinygecko/Makefile b/include/libopencm3/efm32/tinygecko/Makefile
new file mode 100644
index 0000000..4ac5347
--- /dev/null
+++ b/include/libopencm3/efm32/tinygecko/Makefile
@@ -0,0 +1,2 @@
+nvic.h: irq.yaml
+ ./irq2nvic_h
diff --git a/include/libopencm3/efm32/tinygecko/irq.h b/include/libopencm3/efm32/tinygecko/irq.h
deleted file mode 100644
index f5263ae..0000000
--- a/include/libopencm3/efm32/tinygecko/irq.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2012 chrysn <chrysn@fsfe.org>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/** @file
- *
- * Definitions of interrupt names on EFM32 Tiny Gecko systems
- *
- * The names and numbers are taken from d0034_efm32tg_reference_manual.pdf table 4.1.
- */
-
-#ifndef LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H
-#define LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H
-
-#define IRQ_DMA 0
-#define IRQ_GPIO_EVEN 1
-#define IRQ_TIMER0 2
-#define IRQ_USART0_RX 3
-#define IRQ_USART0_TX 4
-#define IRQ_ACMP01 5
-#define IRQ_ADC0 6
-#define IRQ_DAC0 7
-#define IRQ_I2C0 8
-#define IRQ_GPIO_ODD 9
-#define IRQ_TIMER1 10
-#define IRQ_USART1_RX 11
-#define IRQ_USART1_TX 12
-#define IRQ_LESENSE 13
-#define IRQ_LEUART0 14
-#define IRQ_LETIMER0 15
-#define IRQ_PCNT0 16
-#define IRQ_RTC 17
-#define IRQ_CMU 18
-#define IRQ_VCMP 19
-#define IRQ_LCD 20
-#define IRQ_MSC 21
-#define IRQ_AES 22
-#define IRQ_COUNT 23 /**< See also d0002_efm32_cortex-m3_reference_manual.pdf's table 1.1's "number of interrupts" line, which shows that there are really no more interrupts and it is sufficient to allocate only 23 slots. */
-
-#define WEAK __attribute__ ((weak))
-
-void WEAK dma_isr(void);
-void WEAK gpio_even_isr(void);
-void WEAK timer0_isr(void);
-void WEAK usart0_rx_isr(void);
-void WEAK usart0_tx_isr(void);
-void WEAK acmp01_isr(void);
-void WEAK adc0_isr(void);
-void WEAK dac0_isr(void);
-void WEAK i2c0_isr(void);
-void WEAK gpio_odd_isr(void);
-void WEAK timer1_isr(void);
-void WEAK usart1_rx_isr(void);
-void WEAK usart1_tx_isr(void);
-void WEAK lesense_isr(void);
-void WEAK leuart0_isr(void);
-void WEAK letimer0_isr(void);
-void WEAK pcnt0_isr(void);
-void WEAK rtc_isr(void);
-void WEAK cmu_isr(void);
-void WEAK vcmp_isr(void);
-void WEAK lcd_isr(void);
-void WEAK msc_isr(void);
-void WEAK aes_isr(void);
-
-#pragma weak dma_isr = blocking_handler
-#pragma weak gpio_even_isr = blocking_handler
-#pragma weak timer0_isr = blocking_handler
-#pragma weak usart0_rx_isr = blocking_handler
-#pragma weak usart0_tx_isr = blocking_handler
-#pragma weak acmp01_isr = blocking_handler
-#pragma weak adc0_isr = blocking_handler
-#pragma weak dac0_isr = blocking_handler
-#pragma weak i2c0_isr = blocking_handler
-#pragma weak gpio_odd_isr = blocking_handler
-#pragma weak timer1_isr = blocking_handler
-#pragma weak usart1_rx_isr = blocking_handler
-#pragma weak usart1_tx_isr = blocking_handler
-#pragma weak lesense_isr = blocking_handler
-#pragma weak leuart0_isr = blocking_handler
-#pragma weak letimer0_isr = blocking_handler
-#pragma weak pcnt0_isr = blocking_handler
-#pragma weak rtc_isr = blocking_handler
-#pragma weak cmu_isr = blocking_handler
-#pragma weak vcmp_isr = blocking_handler
-#pragma weak lcd_isr = blocking_handler
-#pragma weak msc_isr = blocking_handler
-#pragma weak aes_isr = blocking_handler
-
-#define IRQ_HANDLERS \
- [IRQ_DMA] = dma_isr, \
- [IRQ_GPIO_EVEN] = gpio_even_isr, \
- [IRQ_TIMER0] = timer0_isr, \
- [IRQ_USART0_RX] = usart0_rx_isr, \
- [IRQ_USART0_TX] = usart0_tx_isr, \
- [IRQ_ACMP01] = acmp01_isr, \
- [IRQ_ADC0] = adc0_isr, \
- [IRQ_DAC0] = dac0_isr, \
- [IRQ_I2C0] = i2c0_isr, \
- [IRQ_GPIO_ODD] = gpio_odd_isr, \
- [IRQ_TIMER1] = timer1_isr, \
- [IRQ_USART1_RX] = usart1_rx_isr, \
- [IRQ_USART1_TX] = usart1_tx_isr, \
- [IRQ_LESENSE] = lesense_isr, \
- [IRQ_LEUART0] = leuart0_isr, \
- [IRQ_LETIMER0] = letimer0_isr, \
- [IRQ_PCNT0] = pcnt0_isr, \
- [IRQ_RTC] = rtc_isr, \
- [IRQ_CMU] = cmu_isr, \
- [IRQ_VCMP] = vcmp_isr, \
- [IRQ_LCD] = lcd_isr, \
- [IRQ_MSC] = msc_isr, \
- [IRQ_AES] = aes_isr,
-
-#endif
diff --git a/include/libopencm3/efm32/tinygecko/irq.yaml b/include/libopencm3/efm32/tinygecko/irq.yaml
new file mode 100644
index 0000000..16fa69c
--- /dev/null
+++ b/include/libopencm3/efm32/tinygecko/irq.yaml
@@ -0,0 +1,28 @@
+includeguard: LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H
+partname_humanreadable: EFM32 Tiny Gecko series
+partname_doxygen: EFM32TG
+# The names and sequence are taken from d0034_efm32tg_reference_manual.pdf table 4.1.
+irqs:
+ - dma
+ - gpio_even
+ - timer0
+ - usart0_rx
+ - usart0_tx
+ - acmp01
+ - adc0
+ - dac0
+ - i2c0
+ - gpio_odd
+ - timer1
+ - usart1_rx
+ - usart1_tx
+ - lesense
+ - leuart0
+ - letimer0
+ - pcnt0
+ - rtc
+ - cmu
+ - vcmp
+ - lcd
+ - msc
+ - aes
diff --git a/include/libopencm3/efm32/tinygecko/irq2nvic_h b/include/libopencm3/efm32/tinygecko/irq2nvic_h
new file mode 100755
index 0000000..a7df16e
--- /dev/null
+++ b/include/libopencm3/efm32/tinygecko/irq2nvic_h
@@ -0,0 +1,92 @@
+#!/usr/bin/env python
+
+# This file is part of the libopencm3 project.
+#
+# Copyright (C) 2012 chrysn <chrysn@fsfe.org>
+#
+# This library is free software: you can redistribute it and/or modify
+# it under the terms of the GNU Lesser General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public License
+# along with this library. If not, see <http://www.gnu.org/licenses/>.
+
+import sys
+import yaml
+
+template = '''\
+/* This file is part of the libopencm3 project.
+ *
+ * It was generated by the irq2nvic_h script.
+ */
+
+#ifndef {includeguard}
+#define {includeguard}
+
+/** @defgroup CM3_nvic_defines_{partname_doxygen} User interrupts for {partname_humanreadable}
+ @ingroup CM3_nvic_defines
+
+ @{{*/
+
+{irqdefinitions}
+
+#define NVIC_IRQ_COUNT {irqcount}
+
+/**@}}*/
+
+#define WEAK __attribute__ ((weak))
+
+/** @defgroup CM3_nvic_isrprototypes_{partname_doxygen} User interrupt service routines (ISR) prototypes for {partname_humanreadable}
+ @ingroup CM3_nvic_isrprototypes
+
+ @{{*/
+
+{isrprototypes}
+
+/**@}}*/
+
+/** @defgroup CM3_nvic_isrpragmas_{partname_doxygen} User interrupt service routines (ISR) defaults for {partname_humanreadable}
+ @ingroup CM3_nvic_isrpragmas
+
+ @{{*/
+
+{isrpragmas}
+
+/**@}}*/
+
+/* Initialization template for the interrupt vector table. This definition is
+ * used by the startup code generator (vector.c) to set the initial values for
+ * the interrupt handling routines to the chip family specific _isr weak
+ * symbols. */
+
+#define IRQ_HANDLERS \\
+ {vectortableinitialization}
+
+#endif /* {includeguard} */
+'''
+
+def convert(infile, outfile):
+ data = yaml.load(infile)
+
+ irq2name = list(enumerate(data['irqs']) if isinstance(data['irqs'], list) else data['irqs'].items())
+ irqnames = [v for (k,v) in irq2name]
+
+ data['irqdefinitions'] = "\n".join('#define NVIC_%s_IRQ %d'%(v.upper(),k) for (k,v) in irq2name)
+ data['irqcount'] = len(irq2name) # FIXME: what if it's a sparse dictionary?
+ data['isrprototypes'] = "\n".join('void WEAK %s_isr(void);'%name.lower() for name in irqnames)
+ data['isrpragmas'] = "\n".join('#pragma weak %s_isr = blocking_handler'%name.lower() for name in irqnames)
+ data['vectortableinitialization'] = ', \\\n '.join('[NVIC_%s_IRQ] = %s_isr'%(name.upper(), name.lower()) for name in irqnames)
+
+ outfile.write(template.format(**data))
+
+def main():
+ convert(open('irq.yaml'), open('nvic.h', 'w'))
+
+if __name__ == "__main__":
+ main()
diff --git a/include/libopencm3/lpc43xx/nvic.h b/include/libopencm3/lpc43xx/nvic.h
index cdbf070..0fc5cc6 100644
--- a/include/libopencm3/lpc43xx/nvic.h
+++ b/include/libopencm3/lpc43xx/nvic.h
@@ -1,70 +1,3 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
- * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
- * Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef LPC43XX_NVIC_H
-#define LPC43XX_NVIC_H
-
-#include <libopencm3/cm3/common.h>
-#include <libopencm3/cm3/memorymap.h>
-#include <libopencm3/lpc43xx/memorymap.h>
-
-/* --- NVIC Registers ------------------------------------------------------ */
-
-/* ISER: Interrupt Set Enable Registers */
-/* Note: 8 32bit Registers */
-#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4))
-
-/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
-
-/* ICER: Interrupt Clear Enable Registers */
-/* Note: 8 32bit Registers */
-#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4))
-
-/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
-
-/* ISPR: Interrupt Set Pending Registers */
-/* Note: 8 32bit Registers */
-#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4))
-
-/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
-
-/* ICPR: Interrupt Clear Pending Registers */
-/* Note: 8 32bit Registers */
-#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4))
-
-/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
-
-/* IABR: Interrupt Active Bit Register */
-/* Note: 8 32bit Registers */
-#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4))
-
-/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
-
-/* IPR: Interrupt Priority Registers */
-/* Note: 240 8bit Registers */
-#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id)
-
-/* STIR: Software Trigger Interrupt Register */
-#define NVIC_STIR MMIO32(STIR_BASE)
-
/* --- IRQ channel numbers-------------------------------------------------- */
/* Cortex M4 System Interrupts */
@@ -129,23 +62,7 @@
#define NVIC_M4_C_CAN0_IRQ 51
#define NVIC_M4_QEI_IRQ 52
+#define NVIC_IRQ_COUNT 53
+
/* LPC43xx M0 specific user interrupts */
//TODO
-
-/* --- NVIC functions ------------------------------------------------------ */
-
-BEGIN_DECLS
-
-void nvic_enable_irq(u8 irqn);
-void nvic_disable_irq(u8 irqn);
-u8 nvic_get_pending_irq(u8 irqn);
-void nvic_set_pending_irq(u8 irqn);
-void nvic_clear_pending_irq(u8 irqn);
-u8 nvic_get_active_irq(u8 irqn);
-u8 nvic_get_irq_enabled(u8 irqn);
-void nvic_set_priority(u8 irqn, u8 priority);
-void nvic_generate_software_interrupt(u8 irqn);
-
-END_DECLS
-
-#endif
diff --git a/include/libopencm3/stm32/f1/nvic_f1.h b/include/libopencm3/stm32/f1/nvic_f1.h
index 5223bb6..1544e4f 100644
--- a/include/libopencm3/stm32/f1/nvic_f1.h
+++ b/include/libopencm3/stm32/f1/nvic_f1.h
@@ -109,6 +109,8 @@ LGPL License Terms @ref lgpl_license
#define NVIC_CAN2_RX1_IRQ 65
#define NVIC_CAN2_SCE_IRQ 66
#define NVIC_OTG_FS_IRQ 67
+
+#define NVIC_IRQ_COUNT 68
/**@}*/
#endif
diff --git a/include/libopencm3/stm32/f2/nvic_f2.h b/include/libopencm3/stm32/f2/nvic_f2.h
index 2bf2997..65a990d 100644
--- a/include/libopencm3/stm32/f2/nvic_f2.h
+++ b/include/libopencm3/stm32/f2/nvic_f2.h
@@ -109,4 +109,6 @@
#define NVIC_CRYP_IRQ 79
#define NVIC_HASH_RNG_IRQ 80
+#define NVIC_IRQ_COUNT 81
+
#endif
diff --git a/include/libopencm3/stm32/f4/nvic_f4.h b/include/libopencm3/stm32/f4/nvic_f4.h
index 91b6c25..013e3b5 100644
--- a/include/libopencm3/stm32/f4/nvic_f4.h
+++ b/include/libopencm3/stm32/f4/nvic_f4.h
@@ -109,4 +109,6 @@
#define NVIC_CRYP_IRQ 79
#define NVIC_HASH_RNG_IRQ 80
+#define NVIC_IRQ_COUNT 81
+
#endif