aboutsummaryrefslogtreecommitdiff
path: root/src/cortexm3.c
blob: 7d0b4ae96d480f399857113b8a7e51d0e65d64ca (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
/*
 * This file is part of the Black Magic Debug project.
 *
 * Copyright (C) 2011  Black Sphere Technologies Ltd.
 * Written by Gareth McMullin <gareth@blacksphere.co.nz>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

/* This file implements debugging functionality specific to ARM
 * the Cortex-M3 core.  This should be generic to ARMv7-M as it is 
 * implemented according to the "ARMv7-M Architectue Reference Manual",
 * ARM doc DDI0403C.
 *
 * Issues:
 * There are way too many magic numbers used here.
 */
#include <stdio.h>

#include "general.h"
#include "jtagtap.h"
#include "jtag_scan.h"
#include "adiv5.h"
#include "target.h"

#include "cortexm3.h"
#include "lmi.h"
#include "stm32_tgt.h"

static char cm3_driver_str[] = "ARM Cortex-M3";

static void cm3_attach(struct target_s *target);
static void cm3_detach(struct target_s *target);

static int ap_regs_read(struct target_s *target, void *data);
static int ap_regs_write(struct target_s *target, const void *data);
static int ap_pc_write(struct target_s *target, const uint32_t val);

static void cm3_reset(struct target_s *target);
static void ap_halt_resume(struct target_s *target, uint8_t step);
static int ap_halt_wait(struct target_s *target);
static void ap_halt_request(struct target_s *target);
static int cm3_fault_unwind(struct target_s *target);

static int cm3_set_hw_bp(struct target_s *target, uint32_t addr);
static int cm3_clear_hw_bp(struct target_s *target, uint32_t addr);

static int cm3_set_hw_wp(struct target_s *target, uint8_t type, uint32_t addr, uint8_t len);
static int cm3_clear_hw_wp(struct target_s *target, uint8_t type, uint32_t addr, uint8_t len);

static int cm3_check_hw_wp(struct target_s *target, uint32_t *addr);

/* Watchpoint unit status */
static struct wp_unit_s {
	uint32_t addr;
	uint8_t type;
	uint8_t size;
} hw_watchpoint[4];

/* Breakpoint unit status */
static uint32_t hw_breakpoint[6];

int
cm3_probe(struct target_s *target)
{
	target->driver = cm3_driver_str;

	target->attach = cm3_attach;
	target->detach = cm3_detach;

	/* Should probe here to make sure it's Cortex-M3 */
	target->regs_read = ap_regs_read;
	target->regs_write = ap_regs_write;
//	target->pc_read = ap_pc_read;
	target->pc_write = ap_pc_write;

	target->reset = cm3_reset;
	target->halt_request = ap_halt_request;
	target->halt_wait = ap_halt_wait;
	target->halt_resume = ap_halt_resume;
	target->fault_unwind = cm3_fault_unwind;
	target->regs_size = 16<<2;

	/* if not STM32 try LMI */
	if(stm32_probe(target) != 0)
		lmi_probe(target);

	return 0;
}

static void
cm3_attach(struct target_s *target)
{
	struct target_ap_s *t = (void *)target;
	int i;

	target_halt_request(target);
	while(!target_halt_wait(target));

	/* Request halt on reset */
	/* TRCENA | VC_CORERESET */
	adiv5_ap_mem_write(t->ap, 0xE000EDFC, 0x01000401); 

	/* Reset DFSR flags */
	adiv5_ap_mem_write(t->ap, 0xE000ED30UL, 0x1F);

	/* Clear any stale breakpoints */
	for(i = 0; i < 6; i++) {
		adiv5_ap_mem_write(t->ap, 0xE0002008 + i*4, 0);
		hw_breakpoint[i] = 0;
	}

	/* Clear any stale watchpoints */
	for(i = 0; i < 4; i++) {
		adiv5_ap_mem_write(t->ap, 0xE0001028 + i*0x10, 0);
		hw_watchpoint[i].type = 0;
	}

	/* Flash Patch Control Register: set ENABLE */
	adiv5_ap_mem_write(t->ap, 0xE0002000, 3);
	target->set_hw_bp = cm3_set_hw_bp;
	target->clear_hw_bp = cm3_clear_hw_bp;

	/* Data Watchpoint and Trace */
	target->set_hw_wp = cm3_set_hw_wp;
	target->clear_hw_wp = cm3_clear_hw_wp;
	target->check_hw_wp = cm3_check_hw_wp;
}

static void
cm3_detach(struct target_s *target)
{
	struct target_ap_s *t = (void *)target;
	int i;

	/* Clear any stale breakpoints */
	for(i = 0; i < 6; i++)
		adiv5_ap_mem_write(t->ap, 0xE0002008 + i*4, 0);

	/* Clear any stale watchpoints */
	for(i = 0; i < 4; i++) 
		adiv5_ap_mem_write(t->ap, 0xE0001028 + i*0x10, 0);

	/* Disable debug */
	adiv5_ap_mem_write(t->ap, 0xE000EDF0UL, 0xA05F0000UL);
}

static int
ap_regs_read(struct target_s *target, void *data)
{
	struct target_ap_s *t = (void *)target;
	uint32_t *regs = data;
	int i;

	adiv5_ap_write(t->ap, 0x00, 0xA2000052);
	adiv5_dp_low_access(t->ap->dp, 1, 0, 0x04, 0xE000EDF0);
	adiv5_ap_write(t->ap, 0x14, 0); /* Required to switch banks */
	*regs++ = adiv5_dp_read_ap(t->ap->dp, 0x18);
	for(i = 1; i < 16; i++) {
		adiv5_dp_low_access(t->ap->dp, 1, 0, 0x14, i);
		*regs++ = adiv5_dp_read_ap(t->ap->dp, 0x18);
	}

	return 0;
}

static int
ap_regs_write(struct target_s *target, const void *data)
{
	struct target_ap_s *t = (void *)target;
	const uint32_t *regs = data;
	int i;

	adiv5_ap_write(t->ap, 0x00, 0xA2000052);
	adiv5_dp_low_access(t->ap->dp, 1, 0, 0x04, 0xE000EDF0);
	adiv5_ap_write(t->ap, 0x18, *regs++); /* Required to switch banks */
	adiv5_dp_low_access(t->ap->dp, 1, 0, 0x14, 0x10000);
	for(i = 1; i < 16; i++) {
		adiv5_dp_low_access(t->ap->dp, 1, 0, 0x18, *regs++);
		adiv5_dp_low_access(t->ap->dp, 1, 0, 0x14, i | 0x10000);
	}

	return 0;
}

static int
ap_pc_write(struct target_s *target, const uint32_t val)
{
	struct target_ap_s *t = (void *)target;

	adiv5_ap_write(t->ap, 0x00, 0xA2000052);
	adiv5_dp_low_access(t->ap->dp, 1, 0, 0x04, 0xE000EDF0);

	adiv5_ap_write(t->ap, 0x18, val); /* Required to switch banks */
	adiv5_dp_low_access(t->ap->dp, 1, 0, 0x14, 0x1000F);

	return 0;
}

/* The following three routines implement target halt/resume
 * using the core debug registers in the NVIC. */
static void 
cm3_reset(struct target_s *target)
{
	struct target_ap_s *t = (void *)target;

	jtagtap_srst();

	/* Request system reset from NVIC: SRST doesn't work correctly */
	/* This could be VECTRESET: 0x05FA0001 (reset only core)
	 *          or SYSRESETREQ: 0x05FA0004 (system reset)
	 */
	adiv5_ap_mem_write(t->ap, 0xE000ED0C, 0x05FA0004);
	adiv5_ap_mem_write(t->ap, 0xE000ED0C, 0x05FA0001);

	/* FIXME: poll for release from reset! */
	for(int i = 0; i < 10000; i++) asm("nop");

	/* Reset DFSR flags */
	adiv5_ap_mem_write(t->ap, 0xE000ED30UL, 0x1F);
}

static void 
ap_halt_request(struct target_s *target)
{
	struct target_ap_s *t = (void *)target;

	adiv5_ap_mem_write(t->ap, 0xE000EDF0UL, 0xA05F0003UL);
}

static int
ap_halt_wait(struct target_s *target)
{
	struct target_ap_s *t = (void *)target;

	return adiv5_ap_mem_read(t->ap, 0xE000EDF0UL) & 0x20000;
}

static void 
ap_halt_resume(struct target_s *target, uint8_t step)
{
	struct target_ap_s *t = (void *)target;
	static uint8_t old_step = 0;

	/* Disable interrupts while single stepping... */
	if(step != old_step) {
		adiv5_ap_mem_write(t->ap, 0xE000EDF0UL, 
			step?0xA05F000FUL:0xA05F0003UL);
		old_step = step;
	}

	adiv5_ap_mem_write(t->ap, 0xE000EDF0UL, step?0xA05F000DUL:0xA05F0001UL);
}

static int cm3_fault_unwind(struct target_s *target)
{
	struct target_ap_s *t = (void *)target;
	uint32_t dfsr = adiv5_ap_mem_read(t->ap, 0xE000ED30UL); //DFSR
	//gdb_outf("DFSR = 0x%08X\n", dfsr);
	adiv5_ap_mem_write(t->ap, 0xE000ED30UL, dfsr);/* write back to reset */
	if(dfsr & (1 << 3)) {	// VCATCH
		/* Unwind exception */
		uint32_t regs[16];
		uint32_t stack[8];
		/* Read registers for post-exception stack pointer */
		ap_regs_read(target, regs);
		/* Read stack for pre-exception registers */
		target_mem_read_words(target, stack, regs[13], 8 << 2); 
		regs[0] = stack[0];
		regs[1] = stack[1];
		regs[2] = stack[2];
		regs[3] = stack[3];
		regs[12] = stack[4];
		regs[14] = stack[5];
		regs[15] = stack[6];
		/* FIXME: stack[7] contains xPSR when this is supported */

		/* Write pre-exception registers back to core */
		ap_regs_write(target, regs);

		return 1;
	}
	return 0;
}

/* The following routines implement hardware breakpoints.
 * The Flash Patch and Breakpoint (FPB) system is used. */

static int
cm3_set_hw_bp(struct target_s *target, uint32_t addr)
{
	struct target_ap_s *t = (void *)target;
	uint32_t val = addr & 0x1FFFFFFC;
	int i;

	val |= (addr & 2)?0x80000000:0x40000000;
	val |= 1;

	for(i = 0; i < 6; i++) 
		if((hw_breakpoint[i] & 1) == 0) break;
	
	if(i == 6) return -1;

	hw_breakpoint[i] = addr | 1;

	adiv5_ap_mem_write(t->ap, 0xE0002008 + i*4, val);

	return 0;
}

static int
cm3_clear_hw_bp(struct target_s *target, uint32_t addr)
{
	struct target_ap_s *t = (void *)target;
	int i;

	for(i = 0; i < 6; i++)
		if((hw_breakpoint[i] & ~1) == addr) break;

	if(i == 6) return -1;

	hw_breakpoint[i] = 0;

	adiv5_ap_mem_write(t->ap, 0xE0002008 + i*4, 0);

	return 0; 
}


/* The following routines implement hardware watchpoints.
 * The Data Watch and Trace (DWT) system is used. */

static int
cm3_set_hw_wp(struct target_s *target, uint8_t type, uint32_t addr, uint8_t len)
{
	struct target_ap_s *t = (void *)target;
	int i;

	switch(len) { /* Convert bytes size to mask size */
		case 1: len = 0; break;
		case 2: len = 1; break;
		case 4: len = 2; break;
		default:
			return -1;
	}

	switch(type) { /* Convert gdb type to function type */
		case 2: type = 6; break;
		case 3: type = 5; break;
		case 4: type = 7; break;
		default:
			return -1;
	}

	for(i = 0; i < 4; i++) 
		if((hw_watchpoint[i].type) == 0) break;
	
	if(i == 4) return -2;

	hw_watchpoint[i].type = type;
	hw_watchpoint[i].addr = addr;
	hw_watchpoint[i].size = len;

	adiv5_ap_mem_write(t->ap, 0xE0001020 + i*0x10, addr);
	adiv5_ap_mem_write(t->ap, 0xE0001024 + i*0x10, len);
	adiv5_ap_mem_write(t->ap, 0xE0001028 + i*0x10, 0x800 | type);

	return 0;
}

static int
cm3_clear_hw_wp(struct target_s *target, uint8_t type, uint32_t addr, uint8_t len)
{
	struct target_ap_s *t = (void *)target;
	int i;

	switch(len) {
		case 1: len = 0; break;
		case 2: len = 1; break;
		case 4: len = 2; break;
		default:
			return -1;
	}

	switch(type) {
		case 2: type = 6; break;
		case 3: type = 5; break;
		case 4: type = 7; break;
		default:
			return -1;
	}

	for(i = 0; i < 4; i++)
		if((hw_watchpoint[i].addr == addr) &&
		   (hw_watchpoint[i].type == type) &&
		   (hw_watchpoint[i].size == len)) break;

	if(i == 4) return -2;

	hw_watchpoint[i].type = 0;

	adiv5_ap_mem_write(t->ap, 0xE0001028 + i*0x10, 0);

	return 0;
}

static int
cm3_check_hw_wp(struct target_s *target, uint32_t *addr)
{
	struct target_ap_s *t = (void *)target;
	int i;

	for(i = 0; i < 4; i++)
		/* if SET and MATCHED then break */
		if(hw_watchpoint[i].type && 
		   (adiv5_ap_mem_read(t->ap, 0xE0001028 + i*0x10) & 0x01000000))
			break;

	if(i == 4) return 0;

	*addr = hw_watchpoint[i].addr;
	return 1;
}