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authorMike Smith2011-12-26 02:47:38 -0800
committerMike Smith2011-12-26 02:47:38 -0800
commit00651032ad089711926c175bb252f0c76567c82b (patch)
treeee0de43a2e0e1740fe81ac9d431bdbce933cb140 /src/cortexm3.c
parentbc4c87e45b5b9cc72c46993b1b416017fe4b39a6 (diff)
parent4e0cd081b09d9bd3d444062ca1081fa59c31fc0b (diff)
Merge commit '4e0cd081b09d9bd3d444062ca1081fa59c31fc0b'
* commit '4e0cd081b09d9bd3d444062ca1081fa59c31fc0b': Improved magic number garbage in cortexm3.c Cleaned up debug output on linux build. Removed #if LIGHT for unfinished hardware. Implement gdb 'qCRC' packet to support 'compare-sections' command.
Diffstat (limited to 'src/cortexm3.c')
-rw-r--r--src/cortexm3.c33
1 files changed, 17 insertions, 16 deletions
diff --git a/src/cortexm3.c b/src/cortexm3.c
index 0c6e151..1028acf 100644
--- a/src/cortexm3.c
+++ b/src/cortexm3.c
@@ -354,19 +354,19 @@ cm3_regs_read(struct target_s *target, void *data)
unsigned i;
/* FIXME: Describe what's really going on here */
- adiv5_ap_write(t->ap, 0x00, 0xA2000052);
+ adiv5_ap_write(t->ap, ADIV5_AP_CSW, 0xA2000052);
/* Map the banked data registers (0x10-0x1c) to the
* debug registers DHCSR, DCRSR, DCRDR and DEMCR respectively */
- adiv5_dp_low_access(t->ap->dp, 1, 0, 0x04, CM3_DHCSR);
+ adiv5_dp_low_access(t->ap->dp, 1, 0, ADIV5_AP_TAR, CM3_DHCSR);
/* Walk the regnum_cortex_m array, reading the registers it
* calls out. */
- adiv5_ap_write(t->ap, 0x14, regnum_cortex_m[0]); /* Required to switch banks */
- *regs++ = adiv5_dp_read_ap(t->ap->dp, 0x18);
+ adiv5_ap_write(t->ap, ADIV5_AP_DB(1), regnum_cortex_m[0]); /* Required to switch banks */
+ *regs++ = adiv5_dp_read_ap(t->ap->dp, ADIV5_AP_DB(2));
for(i = 1; i < sizeof(regnum_cortex_m) / 4; i++) {
- adiv5_dp_low_access(t->ap->dp, 1, 0, 0x14, regnum_cortex_m[i]);
- *regs++ = adiv5_dp_read_ap(t->ap->dp, 0x18);
+ adiv5_dp_low_access(t->ap->dp, 1, 0, ADIV5_AP_DB(1), regnum_cortex_m[i]);
+ *regs++ = adiv5_dp_read_ap(t->ap->dp, ADIV5_AP_DB(2));
}
return 0;
@@ -380,19 +380,20 @@ cm3_regs_write(struct target_s *target, const void *data)
unsigned i;
/* FIXME: Describe what's really going on here */
- adiv5_ap_write(t->ap, 0x00, 0xA2000052);
+ adiv5_ap_write(t->ap, ADIV5_AP_CSW, 0xA2000052);
/* Map the banked data registers (0x10-0x1c) to the
* debug registers DHCSR, DCRSR, DCRDR and DEMCR respectively */
- adiv5_dp_low_access(t->ap->dp, 1, 0, 0x04, CM3_DHCSR);
+ adiv5_dp_low_access(t->ap->dp, 1, 0, ADIV5_AP_TAR, CM3_DHCSR);
/* Walk the regnum_cortex_m array, writing the registers it
* calls out. */
- adiv5_ap_write(t->ap, 0x18, *regs++); /* Required to switch banks */
- adiv5_dp_low_access(t->ap->dp, 1, 0, 0x14, 0x10000 | regnum_cortex_m[0]);
+ adiv5_ap_write(t->ap, ADIV5_AP_DB(2), *regs++); /* Required to switch banks */
+ adiv5_dp_low_access(t->ap->dp, 1, 0, ADIV5_AP_DB(1), 0x10000 | regnum_cortex_m[0]);
for(i = 1; i < sizeof(regnum_cortex_m) / 4; i++) {
- adiv5_dp_low_access(t->ap->dp, 1, 0, 0x18, *regs++);
- adiv5_dp_low_access(t->ap->dp, 1, 0, 0x14, 0x10000 | regnum_cortex_m[i]);
+ adiv5_dp_low_access(t->ap->dp, 1, 0, ADIV5_AP_DB(2), *regs++);
+ adiv5_dp_low_access(t->ap->dp, 1, 0, ADIV5_AP_DB(1),
+ 0x10000 | regnum_cortex_m[i]);
}
return 0;
@@ -403,11 +404,11 @@ cm3_pc_write(struct target_s *target, const uint32_t val)
{
struct target_ap_s *t = (void *)target;
- adiv5_ap_write(t->ap, 0x00, 0xA2000052);
- adiv5_dp_low_access(t->ap->dp, 1, 0, 0x04, 0xE000EDF0);
+ adiv5_ap_write(t->ap, ADIV5_AP_CSW, 0xA2000052);
+ adiv5_dp_low_access(t->ap->dp, 1, 0, ADIV5_AP_TAR, CM3_DHCSR);
- adiv5_ap_write(t->ap, 0x18, val); /* Required to switch banks */
- adiv5_dp_low_access(t->ap->dp, 1, 0, 0x14, 0x1000F);
+ adiv5_ap_write(t->ap, ADIV5_AP_DB(2), val); /* Required to switch banks */
+ adiv5_dp_low_access(t->ap->dp, 1, 0, ADIV5_AP_DB(1), 0x1000F);
return 0;
}