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authorRichard Eoin Meadows2014-08-22 21:47:47 +0100
committerGareth McMullin2014-09-03 21:17:48 +1200
commit2a444ab1fba19ab21a25f61be3ff10005775334a (patch)
tree05a3b52755abfcec669bbaad67390d0141ad5b68
parente75798f201a0e4e566f09066c96b0637addc23cb (diff)
Fixed SAM D20 support with reset attached.
monitor connect_srst enable can be used to connect to targets that re-use the SWCLK pin
-rw-r--r--src/samd20.c35
1 files changed, 26 insertions, 9 deletions
diff --git a/src/samd20.c b/src/samd20.c
index f8fc119..bdb2ba6 100644
--- a/src/samd20.c
+++ b/src/samd20.c
@@ -235,8 +235,21 @@ samd20_reset(struct target_s *target)
{
ADIv5_AP_t *ap = adiv5_target_ap(target);
- jtagtap_srst(true);
- jtagtap_srst(false);
+ /**
+ * SRST is not asserted here as it appears to reset the adiv5
+ * logic, meaning that subsequent adiv5_* calls PLATFORM_FATAL_ERROR.
+ *
+ * This is ok as normally you can just connect the debugger and go,
+ * but if that's not possible (protection or SWCLK being used for
+ * something else) then having SWCLK low on reset should get you
+ * debug access (cold-plugging). TODO: Confirm this
+ *
+ * See the SAM D20 datasheet ยง12.6 Debug Operation for more
+ * details.
+ *
+ * jtagtap_srst(true);
+ * jtagtap_srst(false);
+ */
/* Read DHCSR here to clear S_RESET_ST bit before reset */
adiv5_ap_mem_read(ap, CORTEXM_DHCSR);
@@ -309,13 +322,17 @@ bool samd20_probe(struct target_s *target)
target->flash_write = samd20_flash_write;
target_add_commands(target, samd20_cmd_list, "SAMD20");
- /* Release the target from extended reset to make attach possible */
- if (adiv5_ap_mem_read(ap, SAMD20_DSU_CTRLSTAT) &
- SAMD20_STATUSA_CRSTEXT) {
-
- /* Write bit to clear from extended reset */
- adiv5_ap_mem_write(ap, SAMD20_DSU_CTRLSTAT,
- SAMD20_STATUSA_CRSTEXT);
+ /* If we're not in reset here */
+ if (!connect_assert_srst) {
+ /* We'll have to release the target from
+ * extended reset to make attach possible */
+ if (adiv5_ap_mem_read(ap, SAMD20_DSU_CTRLSTAT) &
+ SAMD20_STATUSA_CRSTEXT) {
+
+ /* Write bit to clear from extended reset */
+ adiv5_ap_mem_write(ap, SAMD20_DSU_CTRLSTAT,
+ SAMD20_STATUSA_CRSTEXT);
+ }
}
return true;