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authorNicolas Schodet2008-11-27 23:32:40 +0100
committerNicolas Schodet2008-11-27 23:32:40 +0100
commita703e03d9245449e9edf77c595d192ff4c2d2b43 (patch)
tree93e7a549bb9711189d86dfe7eea8ef5e37e9e156 /analog/aux-power/note_programmeur.txt
parentf0befa937a104c76ad8471e889d5fd0e5f0074c2 (diff)
* analog/aux-power:
- imported puiss-barillet from SI2E sources r426.
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+SIGNAL TRANSITION REQUIREMENTS
+To ensure proper internal logic performance, it is good prac-
+tice to avoid aligning the falling and rising edges of input sig-
+nals. A delay of at least 1 Ásec should be incorporated be-
+tween transitions of the Direction, Brake, and/or PWM input
+signals. A conservative approach is be sure there is at least
+500ns delay between the end of the first transition and the
+beginning of the second transition.
+
+