From a703e03d9245449e9edf77c595d192ff4c2d2b43 Mon Sep 17 00:00:00 2001 From: Nicolas Schodet Date: Thu, 27 Nov 2008 23:32:40 +0100 Subject: * analog/aux-power: - imported puiss-barillet from SI2E sources r426. --- analog/aux-power/note_programmeur.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 analog/aux-power/note_programmeur.txt (limited to 'analog/aux-power/note_programmeur.txt') diff --git a/analog/aux-power/note_programmeur.txt b/analog/aux-power/note_programmeur.txt new file mode 100644 index 00000000..5d7a34f0 --- /dev/null +++ b/analog/aux-power/note_programmeur.txt @@ -0,0 +1,10 @@ +SIGNAL TRANSITION REQUIREMENTS +To ensure proper internal logic performance, it is good prac- +tice to avoid aligning the falling and rising edges of input sig- +nals. A delay of at least 1 µsec should be incorporated be- +tween transitions of the Direction, Brake, and/or PWM input +signals. A conservative approach is be sure there is at least +500ns delay between the end of the first transition and the +beginning of the second transition. + + -- cgit v1.2.3