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authorNicolas Schodet2015-10-27 14:48:42 +0100
committerNicolas Schodet2019-10-07 00:44:57 +0200
commit00f3718f1d52cfb3c8fd10e4c454d7486427a4a1 (patch)
treec99831b1dee3b93df98be0ddbf1c15756a2d9529 /ucoo
parent2b964092e2e39114a453ce66c7f9fe83887971f1 (diff)
ucoo/hal/gpio: add AF and analog setting on STM32F4
Diffstat (limited to 'ucoo')
-rw-r--r--ucoo/hal/gpio/gpio.stm32f4.cc30
-rw-r--r--ucoo/hal/gpio/gpio.stm32f4.hh4
2 files changed, 34 insertions, 0 deletions
diff --git a/ucoo/hal/gpio/gpio.stm32f4.cc b/ucoo/hal/gpio/gpio.stm32f4.cc
index 3ee060a..60e3231 100644
--- a/ucoo/hal/gpio/gpio.stm32f4.cc
+++ b/ucoo/hal/gpio/gpio.stm32f4.cc
@@ -76,6 +76,19 @@ dmask_set (uint32_t mask, uint32_t reg, uint32_t bits)
return reg;
}
+/// Set four bits in a register for the corresponding one-bit mask.
+static uint32_t
+qmask_set (uint32_t mask, uint32_t reg, uint32_t bits)
+{
+ uint32_t qshift = mask * mask;
+ qshift *= qshift;
+ uint32_t qmask = qshift | qshift << 1;
+ qmask = qmask | qmask << 2;
+ reg &= ~qmask;
+ reg |= bits * qshift;
+ return reg;
+}
+
void
Gpio::input ()
{
@@ -104,4 +117,21 @@ Gpio::speed (Speed s)
static_cast<uint32_t> (s));
}
+void
+Gpio::af (int num)
+{
+ GPIO_MODER (port_) = dmask_set (mask_, GPIO_MODER (port_), GPIO_MODE_AF);
+ if (mask_ & 0xff)
+ GPIO_AFRL (port_) = qmask_set (mask_, GPIO_AFRL (port_), num);
+ else
+ GPIO_AFRH (port_) = qmask_set (mask_ >> 8, GPIO_AFRH (port_), num);
+}
+
+void
+Gpio::analog ()
+{
+ GPIO_MODER (port_) = dmask_set (mask_, GPIO_MODER (port_),
+ GPIO_MODE_ANALOG);
+}
+
} // namespace ucoo
diff --git a/ucoo/hal/gpio/gpio.stm32f4.hh b/ucoo/hal/gpio/gpio.stm32f4.hh
index 01f3661..fa73fa2 100644
--- a/ucoo/hal/gpio/gpio.stm32f4.hh
+++ b/ucoo/hal/gpio/gpio.stm32f4.hh
@@ -67,6 +67,10 @@ class Gpio : public Io
void pull (Pull dir);
/// Set output speed.
void speed (Speed s);
+ /// Set alternate function.
+ void af (int num);
+ /// Set as analog.
+ void analog ();
private:
/// Port register base address.
const uint32_t port_;