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authorNicolas Schodet2015-10-27 14:47:51 +0100
committerNicolas Schodet2019-10-07 00:44:50 +0200
commit2b964092e2e39114a453ce66c7f9fe83887971f1 (patch)
treebfcf5d746be4a791c1f8561c877411455462bebb /ucoo
parent653106ca9ba17bee5996cccd41bb8e56ce5e4c71 (diff)
lib/libopencm3, ucoo/hal/sdram: update libopencm3
Diffstat (limited to 'ucoo')
-rw-r--r--ucoo/hal/sdram/sdram.stm32f4.cc24
1 files changed, 12 insertions, 12 deletions
diff --git a/ucoo/hal/sdram/sdram.stm32f4.cc b/ucoo/hal/sdram/sdram.stm32f4.cc
index ed1050c..6bd8ba7 100644
--- a/ucoo/hal/sdram/sdram.stm32f4.cc
+++ b/ucoo/hal/sdram/sdram.stm32f4.cc
@@ -66,20 +66,20 @@ Sdram::enable ()
uint32_t sdcr =
FMC_SDCR_RPIPE_NONE
| (clock_div == 2 ? FMC_SDCR_SDCLK_2HCLK : FMC_SDCR_SDCLK_3HCLK)
- | (params_.cas * FMC_SDCR_CAS_SHIFT)
+ | (params_.cas << FMC_SDCR_CAS_SHIFT)
| (params_.banks == 2 ? FMC_SDCR_NB2 : FMC_SDCR_NB4)
| (params_.bits == 8 ? FMC_SDCR_MWID_8b
: (params_.bits == 16 ? FMC_SDCR_MWID_16b : FMC_SDCR_MWID_32b))
- | ((params_.row_bits - 11) * FMC_SDCR_NR_SHIFT)
- | ((params_.col_bits - 8) * FMC_SDCR_NC_SHIFT);
+ | ((params_.row_bits - 11) << FMC_SDCR_NR_SHIFT)
+ | ((params_.col_bits - 8) << FMC_SDCR_NC_SHIFT);
uint32_t sdtr =
- ((params_.trcd - 1) * FMC_SDTR_TRCD_SHIFT)
- | ((params_.trp - 1) * FMC_SDTR_TRP_SHIFT)
- | ((params_.twr - 1) * FMC_SDTR_TWR_SHIFT)
- | ((params_.trc - 1) * FMC_SDTR_TRC_SHIFT)
- | ((params_.tras - 1) * FMC_SDTR_TRAS_SHIFT)
- | ((params_.txsr - 1) * FMC_SDTR_TXSR_SHIFT)
- | ((params_.tmrd - 1) * FMC_SDTR_TMRD_SHIFT);
+ ((params_.trcd - 1) << FMC_SDTR_TRCD_SHIFT)
+ | ((params_.trp - 1) << FMC_SDTR_TRP_SHIFT)
+ | ((params_.twr - 1) << FMC_SDTR_TWR_SHIFT)
+ | ((params_.trc - 1) << FMC_SDTR_TRC_SHIFT)
+ | ((params_.tras - 1) << FMC_SDTR_TRAS_SHIFT)
+ | ((params_.txsr - 1) << FMC_SDTR_TXSR_SHIFT)
+ | ((params_.tmrd - 1) << FMC_SDTR_TMRD_SHIFT);
if (params_.bank == 1)
{
FMC_SDCR1 = sdcr;
@@ -104,7 +104,7 @@ Sdram::enable ()
while (FMC_SDSR & FMC_SDSR_BUSY)
;
FMC_SDCMR = bank | ((params_.init_auto_refresh - 1)
- * FMC_SDCMR_NRFS_SHIFT)
+ << FMC_SDCMR_NRFS_SHIFT)
| FMC_SDCMR_MODE_AUTO_REFRESH;
while (FMC_SDSR & FMC_SDSR_BUSY)
;
@@ -115,7 +115,7 @@ Sdram::enable ()
: SDRAM_MODE_CAS_LATENCY_3)
| SDRAM_MODE_OPERATING_MODE_STANDARD
| SDRAM_MODE_WRITEBURST_MODE_SINGLE;
- FMC_SDCMR = bank | (sdram_mode * FMC_SDCMR_MRD_SHIFT)
+ FMC_SDCMR = bank | (sdram_mode << FMC_SDCMR_MRD_SHIFT)
| FMC_SDCMR_MODE_LOAD_MODE_REGISTER;
// Set refresh rate.
int refresh_interval_ns = params_.tref_ms * 1000000