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authorTat-Chee Wan (USM)2011-04-01 21:08:58 +0800
committerTat-Chee Wan (USM)2011-04-01 21:08:58 +0800
commitf8fc5a561c7c2800e9f366f1470cec6d7884d218 (patch)
tree8bc9f9891031fd62ef4ebed2bb1065195b0489be
parente1e682a8fc5bc7a297fd4544dc7549cd87657f71 (diff)
defined rrx processing logic
-rw-r--r--Debugger/debug_internals.h10
-rw-r--r--Debugger/debug_stub.S29
2 files changed, 32 insertions, 7 deletions
diff --git a/Debugger/debug_internals.h b/Debugger/debug_internals.h
index a5121d7..632ad91 100644
--- a/Debugger/debug_internals.h
+++ b/Debugger/debug_internals.h
@@ -187,6 +187,7 @@
#define CPSR_FIQ 0x00000040
#define CPSR_IRQ 0x00000080
#define CPSR_MODE 0x0000001F
+#define CPSR_COND 0xF0000000
/* ARM Exception Modes */
#define MODE_USR 0x10 /* User mode */
@@ -197,6 +198,15 @@
#define MODE_UND 0x1B /* Undefined mode */
#define MODE_SYS 0x1F /* System mode */
+/* Condition Flags
+ * b31 b30 b29 b28
+ * N Z C V
+ */
+#define CPSR_NFLAG 0x80000000
+#define CPSR_ZFLAG 0x40000000
+#define CPSR_CFLAG 0x20000000
+#define CPSR_VFLAG 0x10000000
+
/*@}*/
/** Debugger State Enums
diff --git a/Debugger/debug_stub.S b/Debugger/debug_stub.S
index 3b1112f..cb9be94 100644
--- a/Debugger/debug_stub.S
+++ b/Debugger/debug_stub.S
@@ -264,6 +264,7 @@ debug_regShiftJumpTable:
.word _reg_lsr /* 01 */
.word _reg_asr /* 02 */
.word _reg_ror /* 03 */
+ .word _reg_rrx /* 04 */
/*
* To determine the next instruction to execute, we need to check current (breakpointed) instruction
@@ -1996,7 +1997,7 @@ _dbg_check_arm_condcode_exit:
/* _arm_rmshifted_val
* Calculate value of Shifted Rm (operand)
* On entry:
- * R0[11:0]: Sifted Rm operand
+ * R0[11:0]: Shifted Rm operand
* On exit:
* R0: value of Shifted Rm
* R1, R2, R3: destroyed
@@ -2009,18 +2010,24 @@ _arm_rmshifted_val:
_getdbgregisterfromindex r2, r0 /* Retrieve Register Rn contents from Index (R2) into R0 */
tst r3, #0x10 /* B4: Immediate (0) or Register (1) shift count */
- moveq r1, r3, lsr #7 /* Immediate shift count, 5 bit unsigned value in R1 */
- beq _arm_calc_shifted_rm_val
+ /* check bitshift op */
+ and r3, r3, #0x60 /* shift type */
+ mov r3, r3, lsr #5 /* convert into shift type jumptable index */
+ bne _arm_get_reg_shift /* Flags set previously via TST B4 */
+_arm_calc_const_shift:
+ movs r1, r3, lsr #7 /* Immediate shift count, 5 bit unsigned value in R1 */
+ bne _arm_calc_shifted_rm_val /* Non-zero shift count, process normally */
+ /* Must check for RRX == ROR #0 */
+ teq r3, #0x3 /* ROR == 0x3 */
+ addeq r3, r3, #1
+ b _arm_calc_shifted_rm_val
_arm_get_reg_shift:
- mov r2, r3, lsr #8 /* Register-based shift count, 4 bit register enum in R2 */
+ mov r2, r3, lsr #8 /* Register-based shift count, 4 bit register enum in R2 */
_regenum2index r2, r2 /* Convert Enum into Index in R2 */
_getdbgregisterfromindex r2, r1 /* Retrieve Register contents from Index (R2) into R1 */
_arm_calc_shifted_rm_val:
- /* check bitshift op */
- and r3, r3, #0x60 /* shift type */
- mov r3, r3, lsr #5 /* convert into index */
_dbg_jumpTableHandler debug_regShiftJumpTable, r2, r3 /* Calculate RmShifted value from R0: Rn Register val, R1: Shift/Rotate val */
ldmfd sp!, {pc}
@@ -2041,6 +2048,14 @@ _reg_ror:
ror r0, r0, r1
bx lr
+_reg_rrx:
+ moveq r2, #DBGSTACK_USERCPSR_INDEX /* convert register enum to Debug Stack index */
+ _getdbgregisterfromindex r2, r1 /* Retrieve CPSR contents from Index (R2) into R1 */
+ ands r1, r1, #CPSR_CFLAG /* Keep C Flag */
+ movne r1, #0x80000000 /* Set B31 if C Flag set */
+ lsr r0, r0, #1 /* Rm >> 1 */
+ orr r0, r0, r1 /* Put C flag into B31 */
+ bx lr
/* _arm_data_instr_handler