aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorTat-Chee Wan (USM)2011-07-06 09:05:33 +0800
committerTat-Chee Wan (USM)2011-07-06 09:05:33 +0800
commit5adc436b9b0f10dc8461570d75bf9d0d4aeb3850 (patch)
treed3cb7d784792a0f7ae750be70338e207d1a76b89
parentb2f8982f8293ed6b875f2251b4a01011d1786428 (diff)
reorder arm opcode decode table entries to check for more specific instr first
ARM BX/BLX instruction share similar opcode prefix with ARM Data instructions. We must check for the BX/BLX instruction first, otherwise the decoder will assume that it is a Data instruction.
-rw-r--r--Debugger/debug_opcodes.S32
1 files changed, 20 insertions, 12 deletions
diff --git a/Debugger/debug_opcodes.S b/Debugger/debug_opcodes.S
index 6f203fd..a2693b4 100644
--- a/Debugger/debug_opcodes.S
+++ b/Debugger/debug_opcodes.S
@@ -541,14 +541,18 @@ debug_dataInstrJumpTable:
* .word IID, IBM, IHA (12 bytes)
*/
+/* WARNING: The sequence of matching instructions is important!
+ * Always check from more specific to more general IBMs
+ * for instructions sharing common opcode prefix bits.
+ */
debug_armDecodeTable:
- .word 0x0000f000, 0x0c00f000, _arm_data_instr_handler /* Data Processing instr with Rd = R15 */
- .word 0x012fff10, 0x0ffffff0, _arm_bx_blx_handler /* BX or BLX. Note v4t does not have BLX instr */
- .word 0x0410f000, 0x0410f000, _arm_ldr_pc_handler /* LDR with Rd = PC */
-/* .word 0x06000010, 0x0e000010, _arm_undef_handler */ /* Undefined instr: shouldn't occur, as it would've been trapped already. See _dbg_following_instruction_addr */
- .word 0x08108000, 0x0e108000, _arm_ldm_pc_handler /* LDM {pc} */
- .word 0x0a000000, 0x0e000000, _arm_b_bl_blx_handler /* B, BL or BLX. Note v4t does not have BLX instr */
- .word 0x0c000000, 0x0c000000, _arm_coproc_swi_handler /* Coprocessor instr or SWI */
+ .word 0x012fff10, 0x0ffffff0, _arm_bx_blx_handler /* [Prefix:00] BX or BLX. Note v4t does not have BLX instr */
+ .word 0x0000f000, 0x0c00f000, _arm_data_instr_handler /* [Prefix:00] Data Processing instr with Rd = R15 */
+/* .word 0x06000010, 0x0e000010, _arm_undef_handler */ /* [Prefix:01] Undefined instr: shouldn't occur, as it would've been trapped already. See _dbg_following_instruction_addr */
+ .word 0x0410f000, 0x0410f000, _arm_ldr_pc_handler /* [Prefix:01] LDR with Rd = PC */
+ .word 0x08108000, 0x0e108000, _arm_ldm_pc_handler /* [Prefix:10] LDM {pc} */
+ .word 0x0a000000, 0x0e000000, _arm_b_bl_blx_handler /* [Prefix:10] B, BL or BLX. Note v4t does not have BLX instr */
+ .word 0x0c000000, 0x0c000000, _arm_coproc_swi_handler /* [Prefix:11] Coprocessor instr or SWI */
.word 0x0,0x0,0x0 /* Null Entry */
/* Thumb Instruction Decode Table
@@ -556,17 +560,21 @@ debug_armDecodeTable:
* .word IHA (8 bytes)
*/
+/* WARNING: The sequence of matching instructions is important!
+ * Always check from more specific to more general IBMs
+ * for instructions sharing common opcode prefix bits.
+ */
debug_thumbDecodeTable:
.hword 0x4700, 0xff07
- .word _thumb_bx_blx_handler /* BX or BLX. Note: Link (L:b7) is not checked in the mask */
+ .word _thumb_bx_blx_handler /* [Prefix:01] BX or BLX. Note: Link (L:b7) is not checked in the mask */
.hword 0xbd00, 0xff00
- .word _thumb_poppc_handler /* PUSH/POP, specifically POP {Rlist,PC} */
+ .word _thumb_poppc_handler /* [Prefix:10] PUSH/POP, specifically POP {Rlist,PC} */
.hword 0xd000, 0xf000
- .word _thumb_bcond_swi_handler /* B<cond> or SWI */
+ .word _thumb_bcond_swi_handler /* [Prefix:11] B<cond> or SWI */
.hword 0xe000, 0xf800
- .word _thumb_b_handler /* B */
+ .word _thumb_b_handler /* [Prefix:11] B */
.hword 0xf000, 0xf000
- .word _thumb_long_bl_blx_handler /* Long BL or BLX (4 bytes) Note: b11 (H) indicates 1st or 2nd instr */
+ .word _thumb_long_bl_blx_handler /* [Prefix:11] Long BL or BLX (4 bytes) Note: b11 (H) indicates 1st or 2nd instr */
.hword 0x0,0x0
.word 0x0 /* Null Entry */