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path: root/polux/linux-2.6.10/drivers/spi/spc300_spi.c
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/*
 * Driver for SPiDCOM SPC300 SPI Controllers
 *
 * (C) Copyright 2009 SPiDCOM Technologies
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/spi/spi.h>

#include <asm/arch/spc300/hardware/spi.h>

/** Registers access macros */
#define spi_readl(port,reg) __raw_readl((port)->regs + SPI_##reg##_OFFSET)
#define spi_writel(port,reg,value) __raw_writel((value), (port)->regs + SPI_##reg##_OFFSET)

/** Transfer group */
struct spc300_transfer {
    uint32_t tot_txlen;
    uint32_t tot_rxlen;
    struct spi_transfer *from;
    struct spi_transfer *to;
};

/** Private data structure */
struct spc300_spi {
    void __iomem* regs;
    int irq;
    struct platform_device *pdev;
    spinlock_t lock;
    struct list_head queue;
    struct workqueue_struct *workqueue;
    struct work_struct work;
    uint8_t busy;
    struct completion done;
};

/** State structure for transfer configuration */
struct spc300_spi_state {
    int bits_per_word;
    int speed_hz;
};

/**
 * SPI interrupt handler.
 * \param  irq  interrupt number.
 * \param  dev_id  private data structure.
 * \return  interrupt error code.
 */
#if 0
static irqreturn_t spc300_spi_interrupt(int irq, void *dev_id)
{
    struct spc300_spi *ss;

    //Check argument
    if(dev_id == NULL)
        return IRQ_NONE;

    ss = (struct spc300_spi *)dev_id;

    //Check interrupt
    if(SPI_BFEXT(RX, spi_readl(ss, REG_STATUS)))
    {
        //Clear interrupt
        spi_writel(ss, REG_IRQ, SPI_BIT(RX));

        //Wake up the work queue
        complete(&ss->done);

        return IRQ_HANDLED;
    }

    //Spurious interrupt, clear all sources
    spi_writel(ss, REG_IRQ, 0xFFFFFFFF);

    return IRQ_NONE;
}
#endif

/**
 * Internal hardware speed setup.
 * \param  ss  spc300 spi structure
 * \param  speed_hz  speed, in Hz
 */
static void internal_set_speed(struct spc300_spi *ss, int speed_hz)
{
    int freq_reg;
    /* Round up divisor to round down frequency. */
    freq_reg = DIV_ROUND_UP (PCLK, speed_hz * 2) - 1;
    /* Handle overflow. */
    if(freq_reg > 127)
        freq_reg = 127;
    spi_writel(ss, FREQ, freq_reg);
}

/**
 * Internal receive command through SPI controller.
 * \param  ss  spc300 spi structure.
 * \param  nbwords  number of words to transfer.
 * \param  bpw  number of bits per word.
 * \param  buffer  buffer pointer for reception.
 */
static void internal_receive(struct spc300_spi *ss, uint32_t nbwords, uint32_t bpw, uint8_t *buffer)
{
    uint32_t words, i;
    uint32_t cur_buf;

    //Activate RX interrupt and wait it
//    spi_writel(ss, REG_MASK, (spi_readl(ss, REG_MASK) & ~(SPI_BIT(RX))));
//    wait_for_completion(&ss->done);
    //Mask RX interrupt
//    spi_writel(ss, REG_MASK, (spi_readl(ss, REG_MASK) | (SPI_BIT(RX))));

    for(words=0 ; words<nbwords ; words++)
    {
        //Wait word
        while(!SPI_BFEXT(RX, spi_readl(ss, REG_STATUS)));

        //Receive one word
        cur_buf = spi_readl(ss, REG_RX);

        //Store value depending on bytes_per_word
        for(i=0 ; i<bpw ; i++)
        {
            *buffer = (uint8_t)(cur_buf);
            cur_buf = (uint32_t)(cur_buf >> 8);
            buffer++;
        }
    }
}

/**
 * Internal send command through SPI controller.
 * \param  ss  spc300 spi structure.
 * \param  nbwords  number of words to transfer.
 * \param  bpw  number of bits per word.
 * \param  buffer  buffer pointer to send.
 */
static void internal_send(struct spc300_spi *ss, uint32_t nbwords, uint32_t bpw, uint8_t *buffer)
{
    uint32_t words, i;
    uint32_t cur_buf;

    //Wait until all was sent
    while(!SPI_BFEXT(EMPT_TX, spi_readl(ss, REG_STATUS)));

    for(words=0 ; words<nbwords ; words++)
    {
        //Create value depending on bytes_per_word
        for(i=0,cur_buf=0 ; i<bpw ; i++)
            cur_buf = ((uint32_t)(cur_buf<<8)) | ((uint32_t)(*(buffer++)));

        //Send one word
        spi_writel(ss, REG_TX, cur_buf);

        //Wait until FIFO is not full
        while(SPI_BFEXT(FULL_TX, spi_readl(ss, REG_STATUS)));
    }
}

/**
 * Change controller configuration for a new chip transfer.
 * \param  spi  spi device.
 * \return  error code.
 */
static int spc300_spi_activate_hw(struct spi_device *spi, uint32_t nbw_tx, uint32_t nbw_rx)
{
    struct spc300_spi *ss;
    struct spc300_spi_state *sss;
    uint32_t mode = 0;
    volatile uint32_t conf;

    //Check argument
    if(spi == NULL)
        return -EINVAL;

    //Restore datas
    ss = spi_master_get_devdata(spi->master);
    sss = spi->controller_state;

    //Set endianness
    if(spi->mode & SPI_LSB_FIRST)
        mode |= SPI_BIT(LSB);
    //Set polarity
    if(spi->mode & SPI_CPOL)
        mode |= SPI_BIT(CPOL);
    //Set phase
    if(spi->mode & SPI_CPHA)
        mode |= SPI_BIT(CPHA);
    //Set 3 wires or not
    if(spi->mode & SPI_3WIRE)
        mode |= SPI_BIT(W3MA);
    //Store mode
    spi_writel(ss, CTRL_CFG, mode);

    //Set clock frequency from state structure
    internal_set_speed (ss, sss->speed_hz);

    //Set bits_per_word from state structure
    spi_writel(ss, CONF_TX, SPI_BF(TX_LENW, sss->bits_per_word));
    spi_writel(ss, CONF_RX, SPI_BF(RX_LENW, sss->bits_per_word));

    //Set chip select
    spi_writel(ss, SER, (1 << spi->chip_select));

    //Clear RX FIFO to be sure that the eventually next RX can be correct
    while(!SPI_BFEXT(EMPT_RX, spi_readl(ss, REG_STATUS)))
    {
        conf = spi_readl(ss, REG_RX);
    }
    if(SPI_BFEXT(RX, spi_readl(ss, REG_IRQ)))
        spi_writel(ss, REG_IRQ, SPI_BIT(RX));

    //Set number of words for group
    conf = spi_readl(ss, CONF_TX);
    spi_writel(ss, CONF_TX, SPI_BFINS(TX_NUMW, nbw_tx, conf));
    conf = spi_readl(ss, CONF_RX);
    spi_writel(ss, CONF_RX, SPI_BFINS(RX_NUMW, nbw_rx, conf));

    return 0;
}

/**
 * Restore controller configuration for the previous chip transfer.
 * \param  spi  spi device.
 * \return  error code.
 */
static int spc300_spi_unactivate_hw(struct spi_device *spi)
{
    struct spc300_spi *ss;
    volatile uint32_t conf;

    //Check argument
    if(spi == NULL)
        return -EINVAL;

    ss = spi_master_get_devdata(spi->master);

    //Unselect chip
    spi_writel(ss, SER, 0);

    //Set number of words to 0
    conf = spi_readl(ss, CONF_TX);
    spi_writel(ss, CONF_TX, SPI_BFINS(TX_NUMW, 0, conf));
    conf = spi_readl(ss, CONF_RX);
    spi_writel(ss, CONF_RX, SPI_BFINS(RX_NUMW, 0, conf));

    return 0;
}

/**
 * Change configuration controller for a transfer.
 * \param  spi  spi device.
 * \param  tr  spi transfer message.
 * \return  error code.
 */
static int spc300_spi_transfer_setup(struct spi_device *spi, struct spi_transfer *tr)
{
    struct spc300_spi *ss;
    struct spc300_spi_state *sss;

    //Check arguments
    if(spi == NULL)
        return -EINVAL;

    //Restore state datas
    ss = spi_master_get_devdata(spi->master);
    sss = spi->controller_state;

    //Change speed and bits_per_word
    sss->speed_hz = (tr && tr->speed_hz) ? tr->speed_hz : spi->max_speed_hz;
    sss->bits_per_word = (tr &&
                          tr->bits_per_word &&
                          (tr->bits_per_word==8 ||
                           tr->bits_per_word==16 ||
                           tr->bits_per_word==32)
                         ) ? tr->bits_per_word : spi->bits_per_word;

    //Set clock frequency
    internal_set_speed (ss, sss->speed_hz);


    //Set bits_per_word
    spi_writel(ss, CONF_TX, SPI_BF(TX_LENW, sss->bits_per_word));
    spi_writel(ss, CONF_RX, SPI_BF(RX_LENW, sss->bits_per_word));

    return 0;
}

/**
 * Transfer a command through SPI controller.
 * \param  spi  spi device.
 * \param  tr  spi transfers.
 * \param  head head list of spi transfers.
 * \return  transfer length or error code.
 */
static int spc300_spi_transfer_txrx(struct spi_device *spi, struct spc300_transfer *grptr)
{
    struct spc300_spi *ss;
    struct spc300_spi_state *sss;
    struct spi_transfer *tr;
    uint8_t bpw;
    uint32_t tot_nbw_tx, tot_nbw_rx, nbw;
    uint32_t tr_conf_changed=0;
    uint32_t status;

    //Check arguments
    if((spi == NULL) || (grptr == NULL))
        return -EINVAL;

    ss = spi_master_get_devdata(spi->master);
    sss = spi->controller_state;

    //Set total transfer length (always multiple of 8bits)
    bpw = sss->bits_per_word / 8;
    tot_nbw_tx = (grptr->tot_txlen / bpw);
    tot_nbw_rx = (grptr->tot_rxlen / bpw);

    //Check length
    if((tot_nbw_tx > SPI_MAX_WORDS) || (tot_nbw_rx > SPI_MAX_WORDS))
        return -EINVAL;

    tr = grptr->from;

    //Store an eventually specific configuration for this group
    if(tr->bits_per_word || tr->speed_hz)
    {
        if((status = spc300_spi_transfer_setup(spi, tr)) < 0)
            return status;
        tr_conf_changed = 1;
    }

    //Prepare Hardware for this group
    spc300_spi_activate_hw(spi, tot_nbw_tx, tot_nbw_rx);

    //Proceed the group
    while(!(tr->transfer_list.next) ||
          (&tr->transfer_list != (grptr->to)->transfer_list.next))
    {
        nbw = (tr->len / bpw);

        if(tr->tx_buf)
        {
            //Send transfer
            internal_send(ss, nbw, bpw, (uint8_t*)tr->tx_buf);
        }
        else
        {
            //Receive transfer
            internal_receive(ss, nbw, bpw, (uint8_t*)tr->rx_buf);
        }

        //Wait between two transfers
        if(tr->delay_usecs)
            udelay(tr->delay_usecs);

        //Go to the next one
        tr = list_entry(tr->transfer_list.next, typeof(*tr), transfer_list);

    }

    //Wait until all was sent
    while(SPI_BFEXT(BUSY, spi_readl(ss, REG_STATUS)));

    //Restore standard configuration for next group
    if(tr_conf_changed)
    {
        if((status = spc300_spi_transfer_setup(spi, NULL)) < 0)
            return status;
    }

    //Release Hardware
    spc300_spi_unactivate_hw(spi);

    return 0;
}

/**
 * SPI work queue handler.
 * \param  data  data passed to the work.
 */
static void spc300_spi_work(void *data)
{
    struct spc300_spi *ss = (struct spc300_spi *)data;
    struct spi_device *spi;
    struct spi_message *msg;
    struct spi_transfer *tr_prev, *tr_act, *tr_next;
    struct spc300_transfer grptransfer;
    uint8_t bpw;
    int status;
    unsigned long flags;

    spin_lock_irqsave(&ss->lock, flags);
    ss->busy = 1;

    //Empty the message queue
    while(!list_empty(&ss->queue))
    {
        //Restore msg queue
        msg = list_first_entry(&ss->queue, struct spi_message, queue);
        list_del_init(&msg->queue);
        spin_unlock_irqrestore(&ss->lock, flags);
        spi = msg->spi;
        status = 0;

        //First of all, check if list start by a TX
        tr_act = list_first_entry(&msg->transfers, typeof(*tr_act), transfer_list);
        if(tr_act->tx_buf == NULL && tr_act->rx_buf != NULL && tr_act->len)
        {
            dev_err(&spi->dev, "Cannot send a message that start by a RX transfer\n");
            status = -EINVAL;
        }

        if(!status)
        {
            //Check each transfer buffers to see if this IP can manage it
            list_for_each_entry(tr_act, &msg->transfers, transfer_list)
            {
                //Check buffers coherency
                if((tr_act->tx_buf == NULL) && (tr_act->rx_buf == NULL) && tr_act->len)
                {
                    status = -EINVAL;
                    break;
                }

                //This IP cannot manage TX and RX with a unique transfer
                //because we only have a len for the transfer and not a len
                //for tx_buf and rx_buf.
                if((tr_act->tx_buf != NULL) && (tr_act->rx_buf != NULL) && tr_act->len)
                {
                    dev_err(&spi->dev, "Cannot manage TX and RX on a same transfer\n");
                    status = -EINVAL;
                    break;
                }

                //Check length : as we cannot manage really the cs
                //each transfer cannot be split
                if(tr_act->bits_per_word)
                    bpw = tr_act->bits_per_word / 8;
                else
                    bpw = spi->bits_per_word / 8;
                if((tr_act->len / bpw) > SPI_MAX_WORDS)
                {
                    dev_err(&spi->dev, "Cannot manage a transfer length upper than %d bytes\n", SPI_MAX_WORDS*bpw);
                    status = -EINVAL;
                    break;
                }
            }
        }

        if(!status)
        {
            //WARNING:
            //This IP cannot manage the CS so we need to group transfers
            //A group can be :
            //1) a succession of TX
            //2) a TX followed by a succession of RX

            grptransfer.tot_txlen = 0;
            grptransfer.tot_rxlen = 0;
            grptransfer.from = list_entry((&msg->transfers)->next, typeof(*grptransfer.from), transfer_list);

            //Split by groups each transfer
            list_for_each_entry(tr_act, &msg->transfers, transfer_list)
            {
                tr_prev = list_entry(tr_act->transfer_list.prev, typeof(*tr_prev), transfer_list);
                tr_next = list_entry(tr_act->transfer_list.next, typeof(*tr_next), transfer_list);

                if(list_is_last(&tr_act->transfer_list, &msg->transfers))
                {
                    //This is the last transfer we need to transfer the group
                    grptransfer.to = tr_act;
                    if(tr_act->tx_buf)
                        grptransfer.tot_txlen += tr_act->len;
                    else
                        grptransfer.tot_rxlen += tr_act->len;

                    status = spc300_spi_transfer_txrx(spi, &grptransfer);
                    if(status < 0)
                        break;

                    //Update
                    msg->actual_length += grptransfer.tot_txlen;
                    msg->actual_length += grptransfer.tot_rxlen;
                }
                else
                {
                    //It's a TX transfer
                    if(tr_act->tx_buf)
                    {
                        //the following is also a TX group it
                        if(tr_next->tx_buf)
                        {
                            grptransfer.tot_txlen += tr_act->len;
                            continue;
                        }
                        else
                        {
                            //the following is a RX
                            if(&tr_act->transfer_list == msg->transfers.next)
                            {
                                //this is the first transfer no group to transfer
                                grptransfer.tot_txlen += tr_act->len;
                                continue;
                            }
                            else
                            {
                                //transfer the previous group
                                grptransfer.to = tr_prev;
                                grptransfer.tot_txlen += tr_act->len;
                                status = spc300_spi_transfer_txrx(spi, &grptransfer);
                                if(status < 0)
                                    break;
                                //Update
                                msg->actual_length += grptransfer.tot_txlen;
                                msg->actual_length += grptransfer.tot_rxlen;
                                //Prepare for next transfer
                                grptransfer.from = tr_act;
                                grptransfer.tot_txlen = 0;
                                grptransfer.tot_rxlen = 0;
                            }
                        }
                    }
                    else
                    {
                        //the following is also a RX group it
                        if(tr_next->rx_buf)
                        {
                            grptransfer.tot_rxlen += tr_act->len;
                            continue;
                        }
                        else
                        {
                            //the following is a TX so this is the end
                            //of the group : transfer it
                            grptransfer.to = tr_act;
                            grptransfer.tot_rxlen += tr_act->len;
                            status = spc300_spi_transfer_txrx(spi, &grptransfer);
                            if(status < 0)
                                break;
                            //Update
                            msg->actual_length += grptransfer.tot_txlen;
                            msg->actual_length += grptransfer.tot_rxlen;
                            //Prepare for next transfer
                            grptransfer.from = tr_next;
                            grptransfer.tot_txlen = 0;
                            grptransfer.tot_rxlen = 0;
                        }
                    }
                }
            }
        }

        //Update message
        msg->status = status;

        //Call SPI device driver that transfer is ending
        msg->complete(msg->context);

        spin_lock_irqsave(&ss->lock, flags);
    }

    ss->busy = 0;
    spin_unlock_irqrestore(&ss->lock, flags);
}

/**
 * Initialise SPI controller device.
 * \param  spi  spi device structure.
 * \return  error code.
 */
static int spc300_spi_setup(struct spi_device *spi)
{
    struct spc300_spi *ss;
    struct spc300_spi_state *sss;
    unsigned int bits;
    unsigned long flags;

    //Check arguments
    if(spi == NULL)
        return -EINVAL;

    ss = spi_master_get_devdata(spi->master);
    bits = spi->bits_per_word;

    //Check Chip Select
    if(spi->chip_select > spi->master->num_chipselect)
    {
        dev_dbg(&spi->dev, "setup: invalid chipselect %u (%u defined)\n",
                spi->chip_select, spi->master->num_chipselect);
        return -EINVAL;
    }

    //Check bits per word
    if(bits != 8 && bits != 16 && bits != 32)
    {
        dev_dbg(&spi->dev, "setup: invalid bits_per_word %u (only 8,16,32) force 8\n", bits);
        spi->bits_per_word = 8;
    }

    //Check mode
    if((spi->mode & SPI_CS_HIGH) || (spi->mode & SPI_LOOP))
    {
        dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n", SPI_LOOP|SPI_CS_HIGH);
        return -EINVAL;
    }

    //Create a state structure if it doesn't exist
    sss = spi->controller_state;
    if(sss == NULL)
    {
        if((sss = kzalloc(sizeof *sss, GFP_KERNEL)) == NULL)
            return -ENOMEM;
        spi->controller_state = sss;
    }

    //Store this device as the current in use
    sss->bits_per_word = spi->bits_per_word;
    sss->speed_hz = spi->max_speed_hz;

    spin_lock_irqsave(&ss->lock, flags);
    if(!ss->busy)
        spc300_spi_unactivate_hw(spi);
    spin_unlock_irqrestore(&ss->lock, flags);

    return 0;
}

/**
 * Transfer a message (TX and RX) over SPI controller device.
 * \param  spi  spi device structure.
 * \param  msg  message to transfer.
 * \return  error code.
 */
static int spc300_spi_transfer(struct spi_device *spi, struct spi_message *msg)
{
    struct spc300_spi *ss = spi_master_get_devdata(spi->master);
    unsigned long flags;

    msg->actual_length = 0;
    msg->status = -EINPROGRESS;

    //Transfer is made by the workqueue
    spin_lock_irqsave(&ss->lock, flags);
    list_add_tail(&msg->queue, &ss->queue);
    queue_work(ss->workqueue, &ss->work);
    spin_unlock_irqrestore(&ss->lock, flags);

    return 0;
}

/**
 * Uninitialise SPI controller device.
 * \param  spi  spi device structure.
 * \return  error code.
 */
static void spc300_spi_cleanup(struct spi_device *spi)
{
    kfree(spi->controller_state);
}

/**
 * Initialise SPI controller driver.
 * \param  pdev  platform device structure.
 * \return  error code.
 */
static int __init spc300_spi_probe(struct device *dev)
{
    struct resource *regs;
    int irq;
    int ret;
    struct spi_master *master;
    struct spc300_spi *ss;
    struct platform_device *pdev = to_platform_device(dev);

    //Restore Registers base address
    regs = platform_get_resource(pdev, IORESOURCE_IO, 0);
    if(!regs)
        return -ENXIO;

    //Restore IRQ number
    irq = platform_get_irq(pdev, 0);
    if(irq < 0)
        return irq;

    //Create Linux SPI structure for Master device
    ret = -ENOMEM;
    master = spi_alloc_master(&pdev->dev, sizeof *ss);
    if(!master)
        goto out_free;

    master->bus_num = pdev->id;
    master->num_chipselect = 4;
    master->setup = spc300_spi_setup;
    master->transfer = spc300_spi_transfer;
    master->cleanup = spc300_spi_cleanup;
    platform_set_drvdata(pdev, master);

    //Fill our private structure needed by all functions
    ss = spi_master_get_devdata(master);
    ss->pdev = pdev;
    ss->irq = irq;
    ss->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
    if(!ss->regs)
        goto out_free;

    //Register associated IRQ
//    ret = request_irq(irq, spc300_spi_interrupt, 0, "spc300-spictrl", master);
//    if(ret)
//        goto out_unmap_regs;

    spin_lock_init(&ss->lock);
    INIT_LIST_HEAD(&ss->queue);
    INIT_WORK(&ss->work, spc300_spi_work, ss);

    ss->workqueue = create_singlethread_workqueue(master->dev.parent->bus_id);
    if(ss->workqueue == NULL)
    {
        ret = -EBUSY;
        goto out_free_irq;
    }

    //Reset hardware
    RESET_SPI_CTRL();

    //Initialize hardware
    spi_writel(ss, SER, 0); //No chip selected
    spi_writel(ss, MASTER_SLAVE, SPI_BIT(MODE)); //Force Master mode
    spi_writel(ss, CTRL_CFG, SPI_BF(W3SL,0) | //Default 4wires, no gpio emul
                             SPI_BF(W3MA,0) |
                             SPI_BF(EXTIO,0));
    spi_writel(ss, REG_MASK, SPI_BF(EMPT_TX,1) | //Mask all IRQ sources
                             SPI_BF(FULL_TX,1) |
                             SPI_BF(EMPT_RX,1) |
                             SPI_BF(FULL_RX,1) |
                             SPI_BF(RX,1));
    spi_writel(ss, CS_LAT, SPI_BF(CSLAT,0x0)); //0 cycle clock AHB

    dev_info(&pdev->dev, "SPI Controller at 0x%08lx (irq %d)\n", (unsigned long)regs->start, irq);

    //Register SPI Master Controller driver
    ret = spi_register_master(master);
    if(ret)
        goto out_stop_queue;

    return 0;

out_stop_queue:
    destroy_workqueue(ss->workqueue);
out_free_irq:
    free_irq(irq, master);
out_unmap_regs:
    iounmap(ss->regs);
out_free:
    spi_master_put(master);
    return ret;
}

/**
 * Uninitialise SPI controller driver.
 * \param  pdev  platform device structure.
 * \return  error code.
 */
static int __exit spc300_spi_remove(struct platform_device *pdev)
{
    struct spi_master *master = platform_get_drvdata(pdev);
    struct spc300_spi *ss = spi_master_get_devdata(master);
    unsigned long flags;

    //Remove work queue
    flush_workqueue(ss->workqueue);
    destroy_workqueue(ss->workqueue);

    //TODO:Stop hardware
    spin_lock_irqsave(&ss->lock, flags);
    spi_writel(ss, SER, 0); //No chip selected
    spi_writel(ss, REG_MASK, SPI_BF(EMPT_TX,1) | //Mask all IRQ sources
                             SPI_BF(FULL_TX,1) |
                             SPI_BF(EMPT_RX,1) |
                             SPI_BF(FULL_RX,1) |
                             SPI_BF(RX,1));
    spin_unlock_irqrestore(&ss->lock, flags);

    //Unregister IRQ
    free_irq(ss->irq, master);

    //Freeing mapping
    iounmap(ss->regs);

    //Unregister SPI Master Controller device
    spi_unregister_master(master);

    return 0;
}

/** Module structure */
static struct device_driver spc300_spi_driver = {
    .name   = "spc300spictrl",
    .bus    = &platform_bus_type,
    .owner  = THIS_MODULE,
    .probe  = spc300_spi_probe,
    .suspend    = NULL,
    .resume     = NULL,
    .remove     = __exit_p(spc300_spi_remove),
};

/**
 * Module initialization.
 * \return  error code.
 */
static int __init spc300_spi_init(void)
{
    return driver_register(&spc300_spi_driver);
}

/**
 * Module uninitialization.
 * \return  error code.
 */
static void __exit spc300_spi_exit(void)
{
    driver_unregister(&spc300_spi_driver);
}

module_init(spc300_spi_init);
module_exit(spc300_spi_exit);

MODULE_DESCRIPTION("SPiDCOM SPC300 SPI Controller driver");
MODULE_AUTHOR("SPiDCOM Technologies");
MODULE_LICENSE("GPL");