summaryrefslogtreecommitdiff
path: root/polux/linux-2.6.10/drivers/net/synop3504/synop3504_reg.h
blob: 4680f08b8eacbdfd357ea30517aba1943b5946d2 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
#include <asm/io.h>

#ifndef synop3504_reg_h
#define synop3504_reg_h

#ifdef SYNOP_ETH_DEBUG
#define debugp printk
#else
#define debugp(x, ...) 
#endif

#include "synop3504_sys.h" /* System-dependent definitions */

typedef struct SynopsysStruct       /* Synopsys device data */
{
  u32 configBase;   /* base address of Config registers */
  u32 macBase;      /* base address of MAC registers */
  u32 dmaBase;      /* base address of DMA registers */
  u32 phyAddr;      /* PHY device address on MII interface */
} Synopsys;

static void __inline__ SynopsysInit
(
  Synopsys *Dev,          /* Device structure, must be allocated by caller */
  u32 ConfigBase,         /* Base address of Configuration registers */
  u32 MacBase,            /* Base address of MAC registers */
  u32 DmaBase,            /* Base address of DMA registers */
  u32 PhyAddr             /* PHY device address */
){
        Dev->configBase = ConfigBase;
        Dev->macBase = MacBase;
        Dev->dmaBase = DmaBase;
        Dev->phyAddr = PhyAddr;
}


#include "synop3504_regdef.h"
#define AUTOMATIC_PHY_RESOLUTION    -1

static u32 __inline__ SynopsysReadConfigReg( Synopsys *Dev, u32 Reg )
{
  	u32 data;
	data=__raw_readl(Dev->configBase+Reg);
  	//TR( KERN_DEBUG "SynopsysReadConfigReg(%02x)=%08x\n", Reg, data );
  	return data;
}

static void __inline__ SynopsysWriteConfigReg( Synopsys *Dev, u32 Reg, u32 Data )
{
  	//TR( KERN_DEBUG "SynopsysWriteConfigReg(%02x,%08x)\n", Reg, Data );
	__raw_writel(Data,Dev->configBase+Reg);
}

static void __inline__ SynopsysSetConfigReg( Synopsys *Dev, u32 Reg, u32 Data )
{
	u32 data;
	data=__raw_readl(Dev->configBase+Reg);
  	data |= Data;
  	//TR( KERN_DEBUG "SynopsysSetConfigReg(%02x,%08x)=%08x\n", Reg, Data, data );
	__raw_writel(data,Dev->configBase+Reg);
}

static void __inline__ SynopsysClearConfigReg( Synopsys *Dev, u32 Reg, u32 Data )
{
	u32 data;
	data=__raw_readl(Dev->configBase+Reg);
  	data &= ~Data;
  	//TR( KERN_DEBUG "SynopsysClearConfigReg(%02x,%08x)=%08x\n", Reg, Data, data );
	__raw_writel(data,Dev->configBase+Reg);
}

static u32 __inline__ SynopsysReadMacReg( Synopsys *Dev, u32 Reg )
{
 	u32 data; 
  	data=__raw_readl(Dev->macBase+Reg);
  	//TR( KERN_DEBUG "SynopsysReadMacReg(%02x)=%08x\n", Reg, data );
  	return data;
}

static void __inline__ SynopsysWriteMacReg( Synopsys *Dev, u32 Reg, u32 Data )
{
  	//TR( KERN_DEBUG "SynopsysWriteMacReg(%02x,%08x)\n", Reg, Data );
	__raw_writel(Data,Dev->macBase+Reg);
}

static void __inline__ SynopsysSetMacReg( Synopsys *Dev, u32 Reg, u32 Data )
{
  	u32 data;	 
  	data=__raw_readl(Dev->macBase+Reg);
  	data |= Data;
  	//TR( KERN_DEBUG "SynopsysSetMacReg(%02x,%08x)=%08x\n", Reg, Data, data );
	__raw_writel(data,Dev->macBase+Reg);
}

static void __inline__ SynopsysClearMacReg( Synopsys *Dev, u32 Reg, u32 Data )
{
	u32 data;
  	data=__raw_readl(Dev->macBase+Reg);
  	data &= ~Data;
  	//TR( KERN_DEBUG "SynopsysClearMacReg(%02x,%08x)=%08x\n", Reg, Data, data );
	__raw_writel(data,Dev->macBase+Reg);
}

static u32 __inline__ SynopsysReadDmaReg( Synopsys *Dev, u32 Reg )
{
  	u32 data;
	data=__raw_readl(Dev->dmaBase+Reg);
  	//TR( KERN_DEBUG "SynopsysReadDmaReg(%02x)=%08x\n", Reg, data );
  	return data;
}

static void __inline__ SynopsysWriteDmaReg( Synopsys *Dev, u32 Reg, u32 Data )
{
  	//TR( KERN_DEBUG "SynopsysWriteDmaReg(%02x,%08x)\n", Reg, Data );
	__raw_writel(Data,Dev->dmaBase+Reg);
}

static void __inline__ SynopsysSetDmaReg( Synopsys *Dev, u32 Reg, u32 Data )
{
	u32 data;
	data=__raw_readl(Dev->dmaBase+Reg);
  	data |= Data;
  	//TR( KERN_DEBUG "SynopsysSetDmaReg(%02x,%08x)=%08x\n", Reg, Data, data );
	__raw_writel(data,Dev->dmaBase+Reg);
}

static void __inline__ SynopsysClearDmaReg( Synopsys *Dev, u32 Reg, u32 Data )
{
	u32 data;
	data=__raw_readl(Dev->dmaBase+Reg);
  	data &= ~Data;
  	//TR( KERN_DEBUG "SynopsysClearDmaReg(%02x,%08x)=%08x\n", Reg, Data, data );
	__raw_writel(data,Dev->dmaBase+Reg);
}

static u16 __inline__ SynopsysMiiReadPhy (Synopsys * Dev, u32 phyAddr, u8 Reg)
{
    u32 addr;
    u16 data;

    addr = ((phyAddr << GmiiDevShift) & GmiiDevMask) |
        ((Reg << GmiiRegShift) & GmiiRegMask);

    // Enable the phy clock and set the busy bit.
    SynopsysWriteMacReg (Dev, GmacGmiiAddr, (addr | GmiiAppClk4 | GmiiBusy));

    // Wait for busy bit to clear
    while ((SynopsysReadMacReg (Dev, GmacGmiiAddr) & GmiiBusy) == GmiiBusy);

    // Read the phy device data
    data = SynopsysReadMacReg (Dev, GmacGmiiData) & 0xFFFF;

    return data;
}

static u16 __inline__ SynopsysMiiRead (Synopsys * Dev, u8 Reg, s8 PhyAddr_forced)
{
    // If PhyAddr_forced is negative, use the PhyAddr detected
    if (PhyAddr_forced < 0)
        return SynopsysMiiReadPhy (Dev, Dev->phyAddr, Reg);
    else
        return SynopsysMiiReadPhy (Dev, PhyAddr_forced, Reg);
}

static void __inline__ SynopsysMiiWritePhy (Synopsys * Dev, u32 phyAddr, u8 Reg, u16 Data)
{
    u32 addr;

    SynopsysWriteMacReg (Dev, GmacGmiiData, Data);
    addr = ((phyAddr << GmiiDevShift) & GmiiDevMask) |
        ((Reg << GmiiRegShift) & GmiiRegMask) | GmiiWrite;

    // Enable the phy clock and set the busy bit.
    SynopsysWriteMacReg (Dev, GmacGmiiAddr, (addr | GmiiAppClk4 | GmiiBusy));

    // Wait for busy bit to clear
    while ((SynopsysReadMacReg (Dev, GmacGmiiAddr) & GmiiBusy) == GmiiBusy);

}

static void __inline__ SynopsysMiiWrite (Synopsys * Dev, u8 Reg, u16 Data, s8 PhyAddr_forced)
{
    // If PhyAddr_forced is negative, use the PhyAddr detected
    if (PhyAddr_forced <= 0)
        SynopsysMiiWritePhy (Dev, Dev->phyAddr, Reg, Data);
    else
        SynopsysMiiWritePhy (Dev, PhyAddr_forced, Reg, Data);
}

#endif /* __synop3504_reg_h__ */