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/* Cesar project {{{
 *
 * Copyright (C) 2007 Spidcom
 *
 * <<<Licence>>>
 *
 * }}} */
/**
 * \file    lib/src/crc.c
 * \brief   General Cyclic Redundancy Code utilities.
 * \ingroup lib
 */
#include "common/std.h"

#include "lib/crc.h"

/**
 * Reflect the width lowest significant bits in word.
 * \param  word  the word to reflect
 * \param  width  the number of bits
 * \return  the reflected word
 */
extern inline
u32
crc_reflect (u32 word, uint width)
{
    u32 newword;
    uint i;
    /* Please compiler, optimise and inline this or I will have to do it
     * myself: */
    newword = 0;
    for (i = 0; i < width; i++)
    {
        if (word & (1 << i))
            newword |= 1 << (width - i - 1);
    }
    return newword;
}

void
crc_init (crc_t *ctx)
{
    /* OK, for the moment, only support a subset of the general model. */
    dbg_assert_print ((ctx->width == 32 || ctx->width == 24
                       || ctx->width == 16 || ctx->width == 8)
                      && (ctx->refin == true || ctx->refin == false)
                      && (ctx->refout == true || ctx->refout == false),
                      "unsupported model values");
    dbg_assert (ctx->generator);
    dbg_assert (ctx->table.t32);
    /* Compute initial register value. */
    u32 generator = ctx->generator;
    u32 reg_init = ctx->init;
    if (ctx->refin)
    {
        generator = crc_reflect (generator, ctx->width);
        reg_init = crc_reflect (reg_init, ctx->width);
    }
    ctx->reg_init = reg_init;
    /* Generate table. */
    uint i, b;
    u32 reg;
    u32 top = 1 << (ctx->width - 1);
    for (i = 0; i < 256; i++)
    {
        if (ctx->refin)
        {
            reg = i;
            for (b = 0; b < 8; b++)
            {
                if (reg & 1)
                    reg = (reg >> 1) ^ generator;
                else
                    reg >>= 1;
            }
        }
        else
        {
            reg = i << (ctx->width - 8);
            for (b = 0; b < 8; b++)
            {
                if (reg & top)
                    reg = (reg << 1) ^ generator;
                else
                    reg <<= 1;
            }
            reg &= (1 << (ctx->width - 1) << 1) - 1;
        }
        switch (ctx->width)
        {
        case 32:
        case 24:
            ctx->table.t32[i] = reg;
            break;
        case 16:
            ctx->table.t16[i] = reg;
            break;
        case 8:
            ctx->table.t8[i] = reg;
            break;
        }
    }
}

u32
crc_compute_block (const crc_t *ctx, const u8 *block, uint block_size)
{
    dbg_assert (ctx);
    dbg_assert (block || block_size == 0);
    u32 reg;
    reg = crc_compute_begin (ctx);
    reg = crc_compute_continue_block (ctx, reg, block, block_size);
    reg = crc_compute_end (ctx, reg);
    return reg;
}

u32
crc_compute_begin (const crc_t *ctx)
{
    dbg_assert (ctx);
    return ctx->reg_init;
}

u32
crc_compute_continue_block (const crc_t *ctx, u32 reg, const u8 *block,
                            uint block_size)
{
    const u32 *t32;
    const u16 *t16;
    const u8 *t8;
    dbg_assert (ctx);
    dbg_assert (block || block_size == 0);
    if (ctx->refin)
    {
        switch (ctx->width)
        {
        case 32:
        case 24:
            t32 = ctx->table.t32;
            while (block_size--)
                reg = (reg >> 8) ^ t32[(reg ^ *block++) & 0xff];
            break;
        case 16:
            t16 = ctx->table.t16;
            while (block_size--)
                reg = ((reg >> 8) ^ t16[(reg ^ *block++) & 0xff]) & 0xffff;
            break;
        case 8:
            t8 = ctx->table.t8;
            while (block_size--)
                reg = t8[reg ^ *block++];
            break;
        }
    }
    else
    {
        switch (ctx->width)
        {
        case 32:
            t32 = ctx->table.t32;
            while (block_size--)
                reg = (reg << 8) ^ t32[(reg >> 24) ^ *block++];
            break;
        case 24:
            t32 = ctx->table.t32;
            while (block_size--)
                reg = ((reg << 8) ^ t32[(reg >> 16) ^ *block++]) & 0xffffff;
            break;
        case 16:
            t16 = ctx->table.t16;
            while (block_size--)
                reg = ((reg << 8) ^ t16[(reg >> 8) ^ *block++]) & 0xffff;
            break;
        case 8:
            t8 = ctx->table.t8;
            while (block_size--)
                reg = t8[reg ^ *block++];
            break;
        }
    }
    return reg;
}

u32
crc_compute_end (const crc_t *ctx, u32 reg)
{
    dbg_assert (ctx);
    if (ctx->refin != ctx->refout)
        return crc_reflect (reg, ctx->width) ^ ctx->xorout;
    else
        return reg ^ ctx->xorout;
}