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#ifndef PMD_V2_H
#define PMD_V2_H

/* V2 registers */
#define PMD_V2_REGBASE			PMD_V2_BASE
#define PMD_SAFE_REGBASE		(PMD_V2_REGBASE)
#define PMD_DSP_REGBASE			(PMD_V2_REGBASE)
#define PMD_AGC_REGBASE			(PMD_V2_REGBASE+0x001080)
#define PMD_PAF_REGBASE			(PMD_V2_REGBASE+0x001100)
#define PMD_DESYR_REGBASE       (PMD_V2_REGBASE+0x020000)
#define PMD_FEC_DBG_ENB			 (PMD_FEC_REGBASE+0x0200)

#define PMD_ZEROES_AFTER_ADC_OVR	(PMD_V2_REGBASE+0x1094)

#define PMD_V2_BAND0_REAL_COR_OFFSET		0x0000A000
#define PMD_V2_BAND1_REAL_COR_OFFSET		0x0000A100
#define PMD_V2_BAND2_REAL_COR_OFFSET		0x0000A200
#define PMD_V2_BAND3_REAL_COR_OFFSET		0x0000A300
#define PMD_V2_BAND4_REAL_COR_OFFSET		0x0000A400
#define PMD_V2_BAND5_REAL_COR_OFFSET		0x0000A500
#define PMD_V2_BAND6_REAL_COR_OFFSET		0x0000A600
#define PMD_V2_BAND7_REAL_COR_OFFSET		0x0000A700
#define PMD_V2_IMAGINARY_REGS_OFFSET		0x0000C000
#define PMD_V2_FFT_DIVIDER_REGS_OFFSET		0x00009000
#define PMD_V2_MIN_CORRELATION_REGS_OFFSET	0x00008100
#define PMD_V2_MAX_CORRELATION_REGS_OFFSET	0x00008200
#define PMD_V2_STATUS_REGS_OFFSET			0x00004000
#define PMD_V2_DEBUG_REGS_OFFSET			0x00002000
#define PMD_V2_SETUP_REGS_OFFSET			0x00001000

#define DSP_ALBR_ADDR           	 (PMD_DSP_REGBASE+0x2008)
#define DSP_CHMR_ADDR           	 (PMD_DSP_REGBASE+0x0840)
#define DSP_CLBR_ADDR           	 (PMD_DSP_REGBASE+0x2004)
#define DSP_DELTA1_ADDR         	 (PMD_DSP_REGBASE+0x8082)
#define DSP_DELTA2_ADDR         	 (PMD_DSP_REGBASE+0x8084)
#define DSP_DELTA3_ADDR         	 (PMD_DSP_REGBASE+0x8086)
#define DSP_DELTA4_ADDR         	 (PMD_DSP_REGBASE+0x8088)
#define DSP_DELTA5_ADDR         	 (PMD_DSP_REGBASE+0x808A)
#define DSP_DELTA6_ADDR         	 (PMD_DSP_REGBASE+0x808C)
#define DSP_DELTA7_ADDR         	 (PMD_DSP_REGBASE+0x808E)
#define DSP_FBYR_ADDR           	 (PMD_DSP_REGBASE+0x2010)
#define DSP_FLBR_ADDR           	 (PMD_DSP_REGBASE+0x2002)
#define DSP_FSR_ADDR            	 (PMD_DSP_REGBASE+0x4044)
#define DSP_FTR_ADDR            	 (PMD_DSP_REGBASE+0x1004) //SRR
#define DSP_IBYR_ADDR           	 (PMD_DSP_REGBASE+0x2040)
#define DSP_IFSR_ADDR           	 (PMD_DSP_REGBASE+0x4042)
#define DSP_ISFR_ADDR           	 (PMD_DSP_REGBASE+0x4020)
#define DSP_MOR_ADDR            	 (PMD_DSP_REGBASE+0x1008)
#define DSP_OGAIN_ADDR          	 (PMD_DSP_REGBASE+0x1040)
#define DSP_PI1CHAN1R_ADDR      	 (PMD_DSP_REGBASE+0x080A)
#define DSP_PI1CHAN2R_ADDR      	 (PMD_DSP_REGBASE+0x0812)
#define DSP_PI1CHAN3R_ADDR      	 (PMD_DSP_REGBASE+0x081A)
#define DSP_PI1CHAN4R_ADDR      	 (PMD_DSP_REGBASE+0x0822)
#define DSP_PI1CHAN5R_ADDR      	 (PMD_DSP_REGBASE+0x082A)
#define DSP_PI1CHAN6R_ADDR      	 (PMD_DSP_REGBASE+0x0832)
#define DSP_PI1CHAN7R_ADDR      	 (PMD_DSP_REGBASE+0x083A)
#define DSP_PI2CHAN1R_ADDR      	 (PMD_DSP_REGBASE+0x080C)
#define DSP_PI2CHAN2R_ADDR      	 (PMD_DSP_REGBASE+0x0814)
#define DSP_PI2CHAN3R_ADDR      	 (PMD_DSP_REGBASE+0x081C)
#define DSP_PI2CHAN4R_ADDR      	 (PMD_DSP_REGBASE+0x0824)
#define DSP_PI2CHAN5R_ADDR      	 (PMD_DSP_REGBASE+0x082C)
#define DSP_PI2CHAN6R_ADDR      	 (PMD_DSP_REGBASE+0x0834)
#define DSP_PI2CHAN7R_ADDR      	 (PMD_DSP_REGBASE+0x083C)
#define DSP_RBYR_ADDR           	 (PMD_DSP_REGBASE+0x2020)
#define DSP_RPR_ADDR            	 (PMD_DSP_REGBASE+0x1010)
#define DSP_RSR_ADDR            	 (PMD_DSP_REGBASE+0x1020)
#define DSP_STIND1_ADDR         	 (PMD_DSP_REGBASE+0x8102)
#define DSP_STIND2_ADDR         	 (PMD_DSP_REGBASE+0x8104)
#define DSP_STIND3_ADDR         	 (PMD_DSP_REGBASE+0x8106)
#define DSP_STIND4_ADDR         	 (PMD_DSP_REGBASE+0x8108)
#define DSP_STIND5_ADDR         	 (PMD_DSP_REGBASE+0x810A)
#define DSP_STIND6_ADDR         	 (PMD_DSP_REGBASE+0x810C)
#define DSP_STIND7_ADDR         	 (PMD_DSP_REGBASE+0x810E)
#define DSP_STR_ADDR            	 (PMD_DSP_REGBASE+0x1002)
#define DSP_TX_FILTER_TYPE         	 (PMD_DSP_REGBASE+0x2012)
#define DSP_RX_FILTER_TYPE         	 (PMD_DSP_REGBASE+0x2014)
#define DSP_BANDS_TOGETHER         	 (PMD_DSP_REGBASE+0x2018)
#define DSP_START_DETECTION_LEVEL  	 (PMD_DSP_REGBASE+0x2016)
#define DSP_START_COEF            	 (PMD_DSP_REGBASE+0x201C)
#define DSP_START_WIDTH   	         (PMD_DSP_REGBASE+0x201E)
#define DSP_TX_ENABLE_DELAY        	 (PMD_DSP_REGBASE+0x1096)

#define PMD_AGC_MODE_FROZEN			0
#define PMD_AGC_MODE_FIXED			1
#define PMD_AGC_MODE_AUTO			2

#define PMD_AGC_MODE_ADDR			 (PMD_SAFE_REGBASE+0x1080)
#define PMD_AGC_FIXED_GAIN_ADDR		 (PMD_SAFE_REGBASE+0x1082)
#define PMD_AGC_CUR_GAIN_ADDR		 (PMD_SAFE_REGBASE+0x1092)

#endif /* PMD_V2_H */