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#ifndef PLATFORM_TINA_H
#define PLATFORM_TINA_H

/* TOP-LEVEL include to set/change the defines related to memory cunsomption/usage */

#define PB_POOL_RING_SIZE		 		(2048)
#define PB_DMA_POOL_SIZE  				(PB_POOL_RING_SIZE*224)

// WARNING buffer must no cross a 64 KB boundary !

#define DMA_POOL2_BUFFER_SIZE			(32768)
#define DMA_POOL1_BUFFER_SIZE			(4096)
#define DMA_POOL0_BUFFER_SIZE			(256)

#define DMA_RX_POOL2_NB_BUFFER			32
#define DMA_RX_POOL1_NB_BUFFER			32
#define DMA_RX_POOL0_NB_BUFFER			128

#define DMA_TX_POOL2_NB_BUFFER			32
#define DMA_TX_POOL1_NB_BUFFER			32
#define DMA_TX_POOL0_NB_BUFFER			128	

#define DMA_RX_POOL2_SIZE				(DMA_RX_POOL2_NB_BUFFER * DMA_POOL2_BUFFER_SIZE)
#define DMA_RX_POOL1_SIZE				(DMA_RX_POOL1_NB_BUFFER * DMA_POOL1_BUFFER_SIZE)
#define DMA_RX_POOL0_SIZE				(DMA_RX_POOL0_NB_BUFFER * DMA_POOL0_BUFFER_SIZE)

#define DMA_TX_POOL2_SIZE				(DMA_TX_POOL2_NB_BUFFER * DMA_POOL2_BUFFER_SIZE)
#define DMA_TX_POOL1_SIZE				(DMA_TX_POOL1_NB_BUFFER * DMA_POOL1_BUFFER_SIZE)
#define DMA_TX_POOL0_SIZE				(DMA_TX_POOL0_NB_BUFFER * DMA_POOL0_BUFFER_SIZE)

#define DMA_RX_POOL_SIZE				(DMA_RX_POOL2_SIZE + DMA_RX_POOL1_SIZE + DMA_RX_POOL0_SIZE)
#define DMA_TX_POOL_SIZE				(DMA_TX_POOL2_SIZE + DMA_TX_POOL1_SIZE + DMA_TX_POOL0_SIZE)

#define ETH_DMA_ZONE_SIZE	(32768*2)

#define PLC_DMA_ZONE_SIZE	(DMA_RX_POOL_SIZE + DMA_TX_POOL_SIZE + PB_DMA_POOL_SIZE)

#define DMA_ZONE_USED_SIZE	(PLC_DMA_ZONE_SIZE + ETH_DMA_ZONE_SIZE)

#define DMA_ZONE_SIZE		(((DMA_ZONE_USED_SIZE + 0x100000 - 1) / 0x100000) * 0x100000)
#if DMA_ZONE_SIZE !=  0x300000
#error "rrah"
#endif

#define PLC_DMA_RX_BASE		(DMA_zone_base+ETH_DMA_ZONE_SIZE)
#define PLC_DMA_TX_BASE		(PLC_DMA_RX_BASE+DMA_RX_POOL_SIZE)
#define PB_POOL_BASE		(PLC_DMA_TX_BASE+DMA_TX_POOL_SIZE)

#define SKB_RESERVE		(2+32)

#endif /* PLATFORM_TINA_H */