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/*
 * include/asm-arm/arch-spc300/nvram.h
 *
 * Copyright (C) 2009 SPiDCOM Technologies
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __ASM_ARCH_SPC300_NVRAM_H
#define __ASM_ARCH_SPC300_NVRAM_H

// Offset fields
#define NVRAM_MAGIC_OFFSET              0x0
#define NVRAM_PKG_CFG_OFFSET            0x8
#define NVRAM_GPIO_0_7_CFG_OFFSET       0xC
#define NVRAM_GPIO_8_15_CFG_OFFSET      0x10
#define NVRAM_GPIO_ALLOW_DIR_OFFSET     0x14
#define NVRAM_SDRAM_CONFIG_OFFSET       0x18
#define NVRAM_SDRAM_TIMING0_OFFSET      0x1C
#define NVRAM_SDRAM_TIMING1_OFFSET      0x20
#define NVRAM_SDRAM_REFRESH_OFFSET      0x24
#define NVRAM_FLASH_ORG_OFFSET          0x28
#define NVRAM_IMG_0_OFFSET_OFFSET       0x2C
#define NVRAM_NB_IMAGES_OFFSET          0x30
#define NVRAM_PRODUCT_NAME_OFFSET       0x34
#define NVRAM_PRODUCT_PARTNB_OFFSET     0x74
#define NVRAM_PRODUCT_DESC_OFFSET       0xB4
#define NVRAM_SERIAL_NUMBER_OFFSET      0x134
#define NVRAM_ETH_PHY_ADDR_OFFSET       0x174
#define NVRAM_ETH_ADDRESS_OFFSET        0x178
#define NVRAM_RESERVED1_OFFSET          0x17E
#define NVRAM_PLC_ADDRESS_OFFSET        0x180
#define NVRAM_RESERVED2_OFFSET          0x186
#define NVRAM_DEVICE_PASSWORD_OFFSET    0x188
#define NVRAM_OEM_INFO_OFFSET           0x1A8
#define NVRAM_TONEMASK_OFFSET           0x1E8
#define NVRAM_MANUFACTORY_INFO_OFFSET   0x2A8
#define NVRAM_IMG_MAX_SIZE_OFFSET       0x2E8

#define SPC300_NVRAM_MAGIC              "NVRAM\0\0\0"

// Bitfields for pkg_cfg
#define NVRAM_XCLK_SHIFT                0
#define NVRAM_XCLK_MASK                 0x3
#define NVRAM_FREQ_SHIFT                2
#define NVRAM_FREQ_MASK                 0x3
#define NVRAM_PIO_SHIFT                 4
#define NVRAM_PIO_MASK                  0xF
#define NVRAM_ETH_MODE_SHIFT            8
#define NVRAM_ETH_MODE_MASK             0x3

// Values for pkg_cfg
#define NVRAM_XCLK_1875                 0
#define NVRAM_XCLK_25                   1
#define NVRAM_XCLK_375                  2
#define NVRAM_FREQ_100                  0
#define NVRAM_FREQ_125                  1
#define NVRAM_FREQ_133                  2
#define NVRAM_FREQ_150                  3
#define NVRAM_ETH_MODE_MII              0
#define NVRAM_ETH_MODE_RMII             1
#define NVRAM_ETH_MODE_GMII             2

#define NVRAM_GPIO_SHIFT                4
#define NVRAM_GPIO_MASK                 0xF
// Bitfields for gpio 0 to gpio 7
#define NVRAM_GPIO_0_SHIFT              0
#define NVRAM_GPIO_0_MASK               0xF
#define NVRAM_GPIO_1_SHIFT              4
#define NVRAM_GPIO_1_MASK               0xF
#define NVRAM_GPIO_2_SHIFT              8
#define NVRAM_GPIO_2_MASK               0xF
#define NVRAM_GPIO_3_SHIFT              12
#define NVRAM_GPIO_3_MASK               0xF
#define NVRAM_GPIO_4_SHIFT              16
#define NVRAM_GPIO_4_MASK               0xF
#define NVRAM_GPIO_5_SHIFT              20
#define NVRAM_GPIO_5_MASK               0xF
#define NVRAM_GPIO_6_SHIFT              24
#define NVRAM_GPIO_6_MASK               0xF
#define NVRAM_GPIO_7_SHIFT              28
#define NVRAM_GPIO_7_MASK               0xF

// Bitfields for gpio 8 to gpio 15
#define NVRAM_GPIO_8_SHIFT              0
#define NVRAM_GPIO_8_MASK               0xF
#define NVRAM_GPIO_9_SHIFT              4
#define NVRAM_GPIO_9_MASK               0xF
#define NVRAM_GPIO_10_SHIFT             8
#define NVRAM_GPIO_10_MASK              0xF
#define NVRAM_GPIO_11_SHIFT             12
#define NVRAM_GPIO_11_MASK              0xF
#define NVRAM_GPIO_12_SHIFT             16
#define NVRAM_GPIO_12_MASK              0xF
#define NVRAM_GPIO_13_SHIFT             20
#define NVRAM_GPIO_13_MASK              0xF
#define NVRAM_GPIO_14_SHIFT             24
#define NVRAM_GPIO_14_MASK              0xF
#define NVRAM_GPIO_15_SHIFT             28
#define NVRAM_GPIO_15_MASK              0xF

// Bitfields for gpio allowed direction
#define NVRAM_GPIO_DIR_0_SHIFT          0
#define NVRAM_GPIO_DIR_0_MASK           0x3
#define NVRAM_GPIO_DIR_1_SHIFT          2
#define NVRAM_GPIO_DIR_1_MASK           0x3
#define NVRAM_GPIO_DIR_2_SHIFT          4
#define NVRAM_GPIO_DIR_2_MASK           0x3
#define NVRAM_GPIO_DIR_3_SHIFT          6
#define NVRAM_GPIO_DIR_3_MASK           0x3
#define NVRAM_GPIO_DIR_4_SHIFT          8
#define NVRAM_GPIO_DIR_4_MASK           0x3
#define NVRAM_GPIO_DIR_5_SHIFT          10
#define NVRAM_GPIO_DIR_5_MASK           0x3
#define NVRAM_GPIO_DIR_6_SHIFT          12
#define NVRAM_GPIO_DIR_6_MASK           0x3
#define NVRAM_GPIO_DIR_7_SHIFT          14
#define NVRAM_GPIO_DIR_7_MASK           0x3
#define NVRAM_GPIO_DIR_8_SHIFT          16
#define NVRAM_GPIO_DIR_8_MASK           0x3
#define NVRAM_GPIO_DIR_9_SHIFT          18
#define NVRAM_GPIO_DIR_9_MASK           0x3
#define NVRAM_GPIO_DIR_10_SHIFT         20
#define NVRAM_GPIO_DIR_10_MASK          0x3
#define NVRAM_GPIO_DIR_11_SHIFT         22
#define NVRAM_GPIO_DIR_11_MASK          0x3
#define NVRAM_GPIO_DIR_12_SHIFT         24
#define NVRAM_GPIO_DIR_12_MASK          0x3
#define NVRAM_GPIO_DIR_13_SHIFT         26
#define NVRAM_GPIO_DIR_13_MASK          0x3
#define NVRAM_GPIO_DIR_14_SHIFT         28
#define NVRAM_GPIO_DIR_14_MASK          0x3
#define NVRAM_GPIO_DIR_15_SHIFT         30
#define NVRAM_GPIO_DIR_15_MASK          0x3

// Values for gpio allowed direction
#define NVRAM_GPIO_DIR_NONE             0
#define NVRAM_GPIO_DIR_IN               1
#define NVRAM_GPIO_DIR_OUT              2
#define NVRAM_GPIO_DIR_ALL              3

// Bitfields for flash organization
#define NVRAM_FLASH_NB_SECT_SHIFT       0
#define NVRAM_FLASH_NB_SECT_MASK        0xF
#define NVRAM_FLASH_SECT_SZ_SHIFT       4
#define NVRAM_FLASH_SECT_SZ_MASK        0xF

// Values for flash organization
#define NVRAM_FLASH_1_SECT              0
#define NVRAM_FLASH_2_SECT              1
#define NVRAM_FLASH_4_SECT              2
#define NVRAM_FLASH_8_SECT              3
#define NVRAM_FLASH_16_SECT             4
#define NVRAM_FLASH_32_SECT             5
#define NVRAM_FLASH_64_SECT             6
#define NVRAM_FLASH_128_SECT            7
#define NVRAM_FLASH_256_SECT            8
#define NVRAM_FLASH_512_SECT            9
#define NVRAM_FLASH_SECT_64             0
#define NVRAM_FLASH_SECT_128            1
#define NVRAM_FLASH_SECT_256            2


#ifndef __ASSEMBLY__
/* /!\ All values are LITTLE-ENDIAN */
typedef struct
{
    char            magic[8];               // Magic number "NVRAM\0\0\0"
    uint32_t        pkg_cfg;                // SPC300 package configuration register
    uint32_t        gpio_0_7_cfg;           // SPC300 GPIO 0 to 7 configuration register
    uint32_t        gpio_8_15_cfg;          // SPC300 GPIO 8 to 15 configuration register
    uint32_t        gpio_allow_dir;         // SPC300 GPIO allowed direction 0:none 1:in 2:out 3:bi
    uint32_t        sdram_config;           // SPC300 SDRAM configuration register
    uint32_t        sdram_timing0;          // SPC300 SDRAM timing register 0
    uint32_t        sdram_timing1;          // SPC300 SDRAM timing register 1
    uint32_t        sdram_refresh;          // SPC300 SDRAM refresh register
    uint32_t        flash_org;              // Flash organization
    uint32_t        img_0_offset;           // Offset of first image address
    uint32_t        nb_images;              // Max Number of Images present in flash
    char            product_name[64];       // Product short name in string format
    char            product_partnb[64];     // Product part number in string format
    char            product_desc[128];      // Product long description in string format
    char            serial_number[64];      // Product serial number in string format
    uint32_t        eth_phy_addr;           // Address of Ethernet PHY
    unsigned char   eth_address[6];         // Ethernet MAC address
    unsigned char   reserved1[2];
    unsigned char   plc_address[6];         // PowerLine MAC address
    unsigned char   reserved2[2];
    char            device_password[32];    // HomePlugAV device unique password (DPW)
    char            oem_info[64];           // Additional information for OEM
    unsigned char   tonemask[192];          // HomePlugAV tonemask
    char            manufactory_info[64];   // Name of the product manufacturer
    uint32_t        img_max_size;           // Max size of an image in flash
    uint32_t        cpu_partnb;             // SPC3x0 partnb
} spc300_nvram_t; //Currently __attribute__((packed)) not needed

// Bit manipulation macros
#define NVRAM_BIT(name) \
	(1 << NVRAM_##name##_SHIFT)
#define NVRAM_BF(name,value) \
	(((value) & (NVRAM_##name##_MASK)) << NVRAM_##name##_SHIFT)
#define NVRAM_BFEXT(name,value) \
	(((value) >> NVRAM_##name##_SHIFT) & (NVRAM_##name##_MASK))
#define NVRAM_BFINS(name,value,old) \
	( ((old) & ~((NVRAM_##name##_MASK) << NVRAM_##name##_SHIFT)) \
	  | NVRAM_BF(name,value))
#endif
#endif  /* __ASM_ARCH_SPC300_NVRAM_H */