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/*
 * drivers/netspcmac_eth.h
 *
 * Copyright (C) 2009 SPiDCOM Technologies
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * Author(s):
 * June 2009  Drasko DRASKOVIC    <drasko.draskovic@spidcom.com>
 */

#ifndef __DRIVERS_NETSPCMAC_ETH_H
#define __DRIVERS_NETSPCMAC_ETH_H

/*----------------------------------------------------------------------------
 *				MAC BLOCK defines
 *---------------------------------------------------------------------------*/
/* MAC CSR offset */
#define MAC_CONTROL                 0x00000000  /* MAC Control */
#define MAC_FRAME_FILTER            0x00000004  /* MAC frame filter */
#define MAC_HASH_HIGH               0x00000008  /* Multicast Hash Table High */
#define MAC_HASH_LOW                0x0000000c  /* Multicast Hash Table Low */
#define MAC_MII_ADDR                0x00000010  /* MII Address */
#define MAC_MII_DATA                0x00000014  /* MII Data */
#define MAC_FLOW_CONTROL            0x00000018  /* Flow Control */
#define MAC_VLAN                    0x0000001c  /* VLAN Tag */
#define MAC_VERSION                 0x00000020  /* VERSION of the IP core */
#define MAC_INTERRUPT_STATUS        0x00000038  /* Interrupt Status register  */
#define MAC_INTERRUPT_MASK          0x0000003c  /* Interrupt Mask register  */
#define MAC_ADDR_HIGH               0x00000040  /* MAC Address High */
#define MAC_ADDR_LOW                0x00000044  /* MAC Address Low */

//#define MAC_WAKEUP_FILTER           0x00000034  /* Wake-up Frame Filter */
//#define MAC_WAKEUP_CONTROL_STATUS   0x00000038  /* Wake-up Control And Status */


/* MAC CTRL defines */
#define MAC_CONTROL_WD              0x00800000  /* Watchdog Disable */
#define MAC_CONTROL_WE              0x0         /* Watchdog Enable */
#define MAC_CONTROL_JAD             0x00400000  /* Jabber Disable */
#define MAC_CONTROL_JAE             0x0         /* Jabber Enable */
#define MAC_CONTROL_BE              0x00200000  /* Frame Burst Enable */
#define MAC_CONTROL_BD              0x0         /* Frame Burst Disable */
#define MAC_CONTROL_JE              0x00100000  /* Jumbo Frame Enable */
#define MAC_CONTROL_JD              0x0         /* Jumbo Frame Disable */
#define MAC_CONTROL_DCRS            0x00010000  /* Disable Carrier Sense During Transmission */
#define MAC_CONTROL_MII             0x00008000  /* Port Select - MII (10/100 Mbps) */
#define MAC_CONTROL_GMII            0x0         /* Port Select - GMII (1000 Mbps) */
#define MAC_CONTROL_FES100          0x00004000  /* 100Mbps */
#define MAC_CONTROL_FES10           0x0         /* 10Mbs */
#define MAC_CONTROL_DRO              0x00002000  /* Disable recive Own */
#define MAC_CONTROL_ERO              0x0         /* Enable recive Own */
#define MAC_CONTROL_LON             0x00001000  /* Loopback On */
#define MAC_CONTROL_LOFF            0x0         /* Loopback Off */
#define MAC_CONTROL_FD               0x00000800  /* Full  Duplex */
#define MAC_CONTROL_HD              0x0         /* Half  Duplex */
#define MAC_CONTROL_IPC             0x00000400  /* Checksum Offload */
#define MAC_CONTROL_DRTY            0x00000200  /* Disable Retry */
#define MAC_CONTROL_ERTY            0x0         /* Enable Retry */
#define MAC_CONTROL_LUP             0x00000100  /* Link Up */
#define MAC_CONTROL_LDWN            0x0         /* Link Down */
#define MAC_CONTROL_ASTP            0x00000080  /* Automatic Pad Stripping */
#define MAC_CONTROL_BOLMT_10        0x00000000  /* Back Off Limit 10 */
#define MAC_CONTROL_BOLMT_8         0x00000020  /* Back Off Limit 8 */
#define MAC_CONTROL_BOLMT_4         0x00000040  /* Back Off Limit 4 */
#define MAC_CONTROL_BOLMT_1         0x00000060  /* Back Off Limit 1 */
#define MAC_CONTROL_DCE             0x00000010  /* Deferral Check Enable*/
#define MAC_CONTROL_DCD             0x0         /* Deferral Check Disable*/
#define MAC_CONTROL_TE              0x00000008  /* Transmitter Enable */
#define MAC_CONTROL_TD              0x0         /* Transmitter Disable */
#define MAC_CONTROL_RE              0x00000004  /* Receiver Enable */
#define MAC_CONTROL_RD              0x0         /* Receiver Disable */

/* MAC_FRAME_FILTER defines */

#define MAC_FRAME_FILTER_OFF        0x80000000  /* Receive all incoming packets */
#define MAC_FRAME_FILTER_ON         0x0  /* Receive filtered packets only */
#define MAC_FRAME_FILTER_PMON       0x00000010  /* Pass all multicast packets */
#define MAC_FRAME_FILTER_PMOFF      0x0  /* Pass filtered multicast packets */
#define MAC_FRAME_FILTER_IFON       0x00000008  /* Inverse Filtering for DA */
#define MAC_FRAME_FILTER_IFOFF      0x0  /* Normal Filtering for DA */
#define MAC_FRAME_FILTER_HMCON      0x00000004  /* Hash Multicast On */
#define MAC_FRAME_FILTER_HMCOFF     0x0  /* perfect filtering */
#define MAC_FRAME_FILTER_HUCON      0x00000002  /* Hash Unicast On */
#define MAC_FRAME_FILTER_HUCOFF     0x0  /* perfect filtering */
#define MAC_FRAME_FILTER_PRON       0x00000001  /* Receive all valid packets */
#define MAC_FRAME_FILTER_PROFF      0x0         /* Receive filtered packets only */


/* MAC FLOW CTRL defines */
#define MAC_FLOW_CONTROL_PT_MASK  0xffff0000  /* Pause Time Mask */
#define MAC_FLOW_CONTROL_PT_SHIFT 16
#define MAC_FLOW_CONTROL_PCF      0x00000004  /* Pass Control Frames */
#define MAC_FLOW_CONTROL_FCE      0x00000002  /* Flow Control Enable */
#define MAC_FLOW_CONTROL_PAUSE    0x00000001  /* Flow Control Busy ... */

/* MII ADDR  defines */
#define MAC_MII_ADDR_WRITE        0x00000002  /* MII Write */
#define MAC_MII_ADDR_BUSY         0x00000001  /* MII Busy */
#define MAC_MII_ADDR_CSR_CLOCK    0x00000004  /* MII CSR Clock Range set on 100 - 150 Mhz */
#define MAC_MII_ADDR_PHY_MASK     0x0000001f  /* MII PHY address mask */
#define MAC_MII_ADDR_PHY_SHIFT    11          /* MII PHY address shift */
#define MAC_MII_ADDR_REG_MASK     0x0000001f  /* MII register mask */
#define MAC_MII_ADDR_REG_SHIFT    6           /* MII register shift */

/* MAC Management Counters register */
#define MMC_CONTROL               0x00000100  /* MMC Control */
#define MMC_HIGH_INTR             0x00000104  /* MMC High Interrupt */
#define MMC_LOW_INTR              0x00000108  /* MMC Low Interrupt */
#define MMC_HIGH_INTR_MASK        0x0000010c  /* MMC High Interrupt Mask */
#define MMC_LOW_INTR_MASK         0x00000110  /* MMC Low Interrupt Mask */

#define MMC_CONTROL_MAX_FRM_MASK  0x0003ff8   /* Maximum Frame Size */
#define MMC_CONTROL_MAX_FRM_SHIFT 3
#define MMC_CONTROL_MAX_FRAME	  0x7FF

/*----------------------------------------------------------------------------
 *				DMA BLOCK defines
 *---------------------------------------------------------------------------*/
/* DMA CRS Control and Status Register Mapping */
#define DMA_BUS_MODE              0x00001000  /* Bus Mode */
#define DMA_XMT_POLL_DEMAND       0x00001004  /* Transmit Poll Demand */
#define DMA_RCV_POLL_DEMAND       0x00001008  /* Received Poll Demand */
#define DMA_RCV_BASE_ADDR         0x0000100c  /* Receive List Base */
#define DMA_TX_BASE_ADDR          0x00001010  /* Transmit List Base */
#define DMA_STATUS                0x00001014  /* Status Register */
#define DMA_CONTROL               0x00001018  /* Control (Operational Mode) */
#define DMA_INTR_ENA              0x0000101c  /* Interrupt Enable */
#define DMA_MISSED_FRAME_CTR      0x00001020  /* Missed Frame Counter */
#define DMA_CUR_TX_BUF_DESC       0x00001048  /* Current Host Transmit Descriptor Buffer */
#define DMA_CUR_RX_BUF_DESC       0x0000104c  /* Current Host Receive Descriptor Buffer */
#define DMA_CUR_TX_BUF_ADDR       0x00001050  /* Current Host Transmit Address Buffer */
#define DMA_CUR_RX_BUF_ADDR       0x00001054  /* Current Host Receive Address Buffer */

/*  DMA Bus Mode register defines */
#define DMA_BUS_MODE_DBO          0x00100000  /* Descriptor Byte Ordering */
#define DMA_BUS_MODE_PBL_MASK     0x00003f00  /* Programmable Burst Length */
#define DMA_BUS_MODE_PBL_SHIFT    8
#define DMA_BUS_MODE_BLE          0x00000080  /* Big Endian/Little Endian */
#define DMA_BUS_MODE_DSL_MASK     0x0000007c  /* Descriptor Skip Length */
#define DMA_BUS_MODE_DSL_SHIFT    2           /*       (in DWORDS)      */
#define DMA_BUS_MODE_BAR_BUS      0x00000002  /* Bar-Bus Arbitration */
#define DMA_BUS_MODE_SFT_RESET    0x00000001  /* Software Reset */
#define DMA_BUS_MODE_DEFAULT      0x00000000

/* DMA Status register defines */
#define DMA_STATUS_EB_MASK        0x00380000  /* Error Bits Mask */
#define DMA_STATUS_EB_TX_ABORT    0x00080000  /* Error Bits - TX Abort */
#define DMA_STATUS_EB_RX_ABORT    0x00100000  /* Error Bits - RX Abort */
#define DMA_STATUS_TS_MASK        0x00700000  /* Transmit Process State */
#define DMA_STATUS_TS_SHIFT       20
#define DMA_STATUS_RS_MASK        0x000e0000  /* Receive Process State */
#define DMA_STATUS_RS_SHIFT       17
#define DMA_STATUS_NIS            0x00010000  /* Normal Interrupt Summary */
#define DMA_STATUS_AIS            0x00008000  /* Abnormal Interrupt Summary */
#define DMA_STATUS_ERI            0x00004000  /* Early Receive Interrupt */
#define DMA_STATUS_FBI            0x00002000  /* Fatal Bus Error Interrupt */
#define DMA_STATUS_ETI            0x00000400  /* Early Transmit Interrupt */
#define DMA_STATUS_RWT            0x00000200  /* Receive Watchdog Timeout */
#define DMA_STATUS_RPS            0x00000100  /* Receive Process Stopped */
#define DMA_STATUS_RU             0x00000080  /* Receive Buffer Unavailable */
#define DMA_STATUS_RI             0x00000040  /* Receive Interrupt */
#define DMA_STATUS_UNF            0x00000020  /* Transmit Underflow */
#define DMA_STATUS_OVF            0x00000010  /* Receive Overflow */
#define DMA_STATUS_TJT            0x00000008  /* Transmit Jabber Timeout */
#define DMA_STATUS_TU             0x00000004  /* Transmit Buffer Unavailable */
#define DMA_STATUS_TPS            0x00000002  /* Transmit Process Stopped */
#define DMA_STATUS_TI             0x00000001  /* Transmit Interrupt */

/* DMA Control register defines */
#define DMA_CONTROL_TX_SF           0x00200000  /* Transmit Store And Forward */
#define DMA_CONTROL_RX_SF           0x02000000  /* Receive Store And Forward */
#define DMA_CONTROL_TTC_MASK      0x0001c000  /* Transmit Threshold Control */
#define DMA_CONTROL_TTC_32        0x00000000  /* Threshold is 32 DWORDS */
#define DMA_CONTROL_TTC_64        0x00004000  /* Threshold is 64 DWORDS */
#define DMA_CONTROL_TTC_128       0x00008000  /* Threshold is 128 DWORDS */
#define DMA_CONTROL_TTC_256       0x0000c000  /* Threshold is 256 DWORDS */
#define DMA_CONTROL_TTC_18        0x00010000  /* Threshold is 18 DWORDS */
#define DMA_CONTROL_TTC_24        0x00014000  /* Threshold is 24 DWORDS */
#define DMA_CONTROL_TTC__32_      0x00018000  /* Threshold is 32 DWORDS */
#define DMA_CONTROL_TTC_40        0x0001c000  /* Threshold is 40 DWORDS */
#define DMA_CONTROL_ST            0x00002000  /* Start/Stop Transmission */
#define DMA_CONTROL_FUF           0x00000040  /* Forward undersize frames */
#define DMA_CONTROL_SE            0x00000008  /* Stop On Empty */
#define DMA_CONTROL_OSF           0x00000004  /* Operate On 2nd Frame */
#define DMA_CONTROL_SR            0x00000002  /* Start/Stop Receive */

/* DMA Interrupt Enable register defines */
#define DMA_INTR_ENA_NIE          0x00010000  /* Normal Interrupt Summary */
#define DMA_INTR_ENA_AIE          0x00008000  /* Abnormal Interrupt Summary */
#define DMA_INTR_ENA_ERE          0x00004000  /* Early Receive */
#define DMA_INTR_ENA_FBE          0x00002000  /* Fatal Bus Error */
#define DMA_INTR_ENA_ETE          0x00000400  /* Early Transmit */
#define DMA_INTR_ENA_RWE          0x00000200  /* Receive Watchdog */
#define DMA_INTR_ENA_RSE          0x00000100  /* Receive Stopped */
#define DMA_INTR_ENA_RUE          0x00000080  /* Receive Buffer Unavailable */
#define DMA_INTR_ENA_RIE          0x00000040  /* Receive Interrupt */
#define DMA_INTR_ENA_UNE          0x00000020  /* Underflow */
#define DMA_INTR_ENA_OVE          0x00000010  /* Receive Overflow */
#define DMA_INTR_ENA_TJE          0x00000008  /* Transmit Jabber */
#define DMA_INTR_ENA_TUE          0x00000004  /* Transmit Buffer Unavailable */
#define DMA_INTR_ENA_TSE          0x00000002  /* Transmit Stopped */
#define DMA_INTR_ENA_TIE          0x00000001  /* Transmit Interrupt */
/* DMA default interrupt mask */
#define DMA_INTR_DEFAULT_MASK	(DMA_INTR_ENA_NIE | DMA_INTR_ENA_AIE | \
				DMA_INTR_ENA_FBE | DMA_INTR_ENA_RWE | \
				DMA_INTR_ENA_RSE | DMA_INTR_ENA_RUE | \
				DMA_INTR_ENA_RIE | DMA_INTR_ENA_UNE | \
				DMA_INTR_ENA_OVE | DMA_INTR_ENA_TJE | \
				DMA_INTR_ENA_TUE | DMA_INTR_ENA_TSE | \
				/*DMA_INTR_ENA_ERE | DMA_INTR_ENA_ETE | */ \
				DMA_INTR_ENA_TIE)

/*----------------------------------------------------------------------------
 *			    Descriptor defines
 *---------------------------------------------------------------------------*/
/* Common fields */
#define OWN_BIT			         0x80000000  /* Own Bit (owned by hardware) */
#define DES1_CONTROL_CH		      0x01000000  /* Second Address Chained */
#define DES1_CONTROL_TER	      0x02000000  /* End of Ring */
#define DES1_RBS2_SIZE_MASK	   0x003ff800  /* Buffer 2 Size Mask */
#define DES1_RBS2_SIZE_SHIFT	   11          /* Buffer 2 Size Shift */
#define DES1_RBS1_SIZE_MASK	   0x000007ff  /* Buffer 1 Size Mask */
#define DES1_RBS1_SIZE_SHIFT	   0           /* Buffer 1 Size Shift */

/* Receive Descriptor */
#define RDES0_STATUS_FILTER_FAIL  0x40000000  /* Filtering Fail */
#define RDES0_STATUS_FL_MASK      0x3fff0000  /* Frame Length Mask */
#define RDES0_STATUS_FL_SHIFT     16          /* Frame Length Shift */
#define RDES0_STATUS_ES           0x00008000  /* Error Summary */
#define RDES0_STATUS_DE           0x00004000  /* Descriptor Error */
#define RDES0_STATUS_PFE          0x00002000  /* Partial Frame Error */
#define RDES0_STATUS_LENGTH_ERROR 0x00001000  /* Length Error */
#define RDES0_STATUS_RUNT_FRM     0x00000800  /* Runt Frame */
#define RDES0_STATUS_MULTICST_FRM 0x00000400  /* Multicast Frame */
#define RDES0_STATUS_FS           0x00000200  /* First Descriptor */
#define RDES0_STATUS_LS           0x00000100  /* Last Descriptor */
#define RDES0_STATUS_TL           0x00000080  /* Frame Too Long */
#define RDES0_STATUS_COL_SEEN     0x00000040  /* Collision Seen */
#define RDES0_STATUS_FRM_TYPE     0x00000020  /* Frame Type */
#define RDES0_STATUS_RX_WATCHDOG  0x00000010  /* Receive Watchdog */
#define RDES0_STATUS_MII_ERR      0x00000008  /* Report on MII Error */
#define RDES0_STATUS_DRIBBLE      0x00000004  /* Dribbling Bit */
#define RDES0_STATUS_CE           0x00000002  /* CRC Error */
#define RDES0_STATUS_0            0x00000000  /* Always tied to zero */

#define RDES1_CONTROL_DIOC        0x80000000  /* Disable Intr On Completion */

/* Transmit Descriptor */
#define TDES0_STATUS_ES		         0x00008000  /* Error Summary */
#define TDES0_STATUS_LOSS_CARRIER   0x00000800  /* Loss of Carrier */
#define TDES0_STATUS_NO_CARRIER     0x00000400  /* No Carrier */
#define TDES0_STATUS_LATE_COL       0x00000200  /* Late Collision */
#define TDES0_STATUS_EX_COL         0x00000100  /* Excessive Collisions */
#define TDES0_STATUS_HRTBT_FAIL     0x00000080  /* Heartbeat Fail */
#define TDES0_STATUS_COLCNT_MASK    0x00000078  /* Collision Count Mask */
#define TDES0_STATUS_COLCNT_SHIFT   3           /* Collision Count Shift */
#define TDES0_STATUS_EX_DEF         0x00000004  /* Excessive Deferrals */
#define TDES0_STATUS_UF             0x00000002  /* Underflow Error */
#define TDES0_STATUS_DF             0x00000001  /* Deferred */

#define TDES1_CONTROL_IC          0x80000000  /* Interrupt on Completion */
#define TDES1_CONTROL_LS          0x40000000  /* Last Segment */
#define TDES1_CONTROL_FS          0x20000000  /* First Segment */
#define TDES1_CONTROL_AC          0x04000000  /* Add CRC Disable */
#define TDES1_CONTROL_DPD         0x00800000  /* Disable Padding */

#define SPCMAC_READ(REG) readl(CONFIG_SPCMAC_ADDRESS+(REG))
#define SPCMAC_WRITE(V, REG) writel(V, CONFIG_SPCMAC_ADDRESS+(REG))

/* MII interface defns */

#ifndef CONFIG_SPCMAC_MII_POLL_BUSY_DELAY
#define CONFIG_SPCMAC_MII_POLL_BUSY_DELAY 1000
#endif

#ifndef CONFIG_SPCMAC_AUTONEG_TIMEOUT
#define CONFIG_SPCMAC_AUTONEG_TIMEOUT  (4*CFG_HZ) /* ticks */
#endif

#ifndef CONFIG_SPCMAC_TX_TIMEOUT
#define CONFIG_SPCMAC_TX_TIMEOUT  (5*CFG_HZ) /* ticks */
#endif

/*----------------------------------------------------------------------------
 *			    PHY defines
 *---------------------------------------------------------------------------*/
/* PHY register mapping */
#define MII_BMCR            0x00        /* Basic mode control register */
#define MII_BMSR            0x01        /* Basic mode status register  */
#define MII_PHYSID1         0x02        /* PHYS ID 1                   */
#define MII_PHYSID2         0x03        /* PHYS ID 2                   */
#define MII_ADVERTISE       0x04        /* Advertisement control reg   */
#define MII_LPA             0x05        /* Link partner ability reg    */
#define MII_EXPANSION       0x06        /* Expansion register          */
#define MII_MCR_1000        0x09        /* 1000 Control register       */
#define MII_MSR_1000        0x0A        /* 1000 Status register        */
#define MII_EMSR            0x0F        /* Extended Status register    */

#define MII_PHYSPECIFICCTL1     0x10        /* Reg 16 - PHY Specific Control Register1  */
#define MII_PHYLINKSTATUS       0x11        /* Reg 17 - PHY Link Status Register        */
#define MII_PHYSPECIFICCTL2     0x14        /* Reg 20 - PHY Specific Control Register2  */

/* PHY register field masks */
/* Basic mode control register. */
#define BMCR_RESV                   0x003f  /* Unused...                   */
#define BMCR_CTST                   0x0080  /* Collision test              */
#define BMCR_FULLDPLX               0x0100  /* Full duplex                 */
#define BMCR_ANRESTART              0x0200  /* Auto negotiation restart    */
#define BMCR_ISOLATE                0x0400  /* Disconnect from MII -- not supported by IP175C */
#define BMCR_PDOWN                  0x0800  /* Powerdown        */
#define BMCR_ANENABLE               0x1000  /* Enable auto negotiation      */
#define BMCR_LOOPBACK               0x4000  /* TXD loopback bits            */
#define BMCR_RESET                  0x8000  /* Reset                        */
#define BMCR_SPEED_SELECTION_LSB    0x2000  /* Speed Selection MSB          */
#define BMCR_SPEED_SELECTION_MSB    0x0040  /* Speed Selection LSB          */

/* NOTE : ALWAYS CLEAR SPEED_SELECTION MSB AND LSB BITS BEFORE SETTING SPEED    */
#define BMCR_SPEED1000              BMCR_SPEED_SELECTION_MSB    /* lsb:msb = 1:0 -> 1000Mb/s        */
#define BMCR_SPEED100               BMCR_SPEED_SELECTION_LSB    /* lsb:msb = 0:1 -> 100Mb/s         */
#define BMCR_SPEED10                0x0                         /* lsb:msb = 0:0 -> 10Mb/s          */

/* Basic mode status register. */
#define BMSR_ERCAP              0x0001  /* Ext-reg capability          */
#define BMSR_JCD                0x0002  /* Jabber detected             */
#define BMSR_LSTATUS            0x0004  /* Link status                 */
#define BMSR_ANEGCAPABLE        0x0008  /* Able to do auto-negotiation */
#define BMSR_RFAULT             0x0010  /* Remote fault detected       */
#define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
#define BMSR_RESV               0x06c0  /* Unused...                   */
#define BMSR_EXT                0x0100  /* Support extended mode (Giga)*/
#define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
#define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
#define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
#define BMSR_100FULL            0x4000  /* Can do 100mbps, full-duplex */
#define BMSR_100BASE4           0x8000  /* Can do 100mbps, 4k packets  */

/* Advertisement control register. */
#define ADVERTISE_SLCT          0x001f  /* Selector bits               */
#define ADVERTISE_CSMA          0x0001  /* Only selector supported     */
#define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
#define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
#define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
#define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
#define ADVERTISE_100BASE4      0x0200  /* Try for 100mbps 4k packets  */
#define ADVERTISE_RESV1         0x1c00  /* Unused...                   */
#define ADVERTISE_RFAULT        0x2000  /* Say we can detect faults    */
#define ADVERTISE_RESV2         0x4000  /* Reserved by IEEE, write as 0 or ignore */
#define ADVERTISE_NPAGE         0x8000  /* Next page bit               */

#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
                        ADVERTISE_CSMA)
#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
                       ADVERTISE_100HALF | ADVERTISE_100FULL)

/* Link partner ability register. */
#define LPA_SLCT                 0x001f   /* Same as advertise selector  */
#define LPA_10HALF               0x0020   /* Can do 10mbps half-duplex   */
#define LPA_10FULL               0x0040   /* Can do 10mbps full-duplex   */
#define LPA_100HALF              0x0080   /* Can do 100mbps half-duplex  */
#define LPA_100FULL              0x0100   /* Can do 100mbps full-duplex  */
#define LPA_100BASE4             0x0200   /* Can do 100mbps 4k packets   */
#define MII_ADVERTISE_PAUSE      0x0400   /* Supports the pause command */
#define LPA_RESV                 0x1c00   /* Unused...                   */
#define LPA_RFAULT               0x2000   /* Link partner faulted        */
#define LPA_LPACK                0x4000   /* Link partner acked us       */
#define LPA_NPAGE                0x8000   /* Next page bit               */

#define LPA_DUPLEX              (LPA_10FULL | LPA_100FULL)
#define LPA_100                 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)

/* Auto-neg expansion register */
#define ANEXP_LP_AUTONEG_ABLE   0x01        /* Link partner supports auto-negotiation */

/* 1000 mode control register. */
#define ADVERTISE_1000HALF       0x0100  /* Can do 1000mbps, half-duplex */
#define ADVERTISE_1000FULL       0x0200  /* Can do 1000mbps, full-duplex */
#define PORT_TYPE                0x0400  /* Multi/single port            */
#define CONF_VAL                 0x0800  /* Master/Slave configuration   */
#define MAN_CONF_VAL             0x1000  /* Activate Manual configuration*/

/* 1000 mode status register. */
#define LPA_1000HALF             0x0400  /* Can do 1000mbps half-duplex */
#define LPA_1000FULL             0x0800  /* Can do 1000mbps full-duplex */
#define REMOTE_RX                0x1000  /* Remote receiver             */
#define LOCAL_RX                 0x2000  /* Local receiver              */
#define M_S_CONF                 0x4000  /* Master/Slave configuration  */
#define M_S_CONF_FAULT           0x8000  /* Master/Slave config fault   */

/* Extended mode status register. */
#define EMSR_1000HALF            0x1000  /* Can do 1000mbps, half-duplex */
#define EMSR_1000FULL            0x2000  /* Can do 1000mbps, full-duplex */

/* Bit fields for MII_PHYSID */
#define PHYSID_GET_ID(id1, id2)  (id1 << 16 | id2)
#define PHYSID_GET_OUI(id)       ((id >> 10) & 0x00FFFFFF)
#define PHYSID_GET_MODEL(id)     ((id >>  4) & 0x0000003F)
#define PHYSID_GET_REV(id)       ((id >>  0) & 0x0000000F)

/* Some PHY model references */
#define ICPLUS_OUI               0x0090C3
#define ICPLUS_IP175             0x18
#define ICPLUS_IP1001            0x19
#define VITESSE_OUI              0x0001C1
#define VITESSE_VSC8601          0x02

/* internal IP175D PHY ID */
#define ICPLUS_ID_IP175D         0x175D

/* Allocate DMA coherent memory */
#define DMA_ALLOC(LEN) malloc(LEN)
#define DMA_FREE(P) free(P)

#endif /* __DRIVERS_NETSPCMAC_ETH_H */