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/*
 * cpu/spc300/spcpio.S
 *
 * Copyright (C) 2012 SPiDCOM Technologies
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <asm/arch/hardware.h>
#include <asm/arch/nvram.h>

/* Skip file if not using SPC GPIO and PIO regbank registers. */
#ifdef CONFIG_CHIP_FEATURE_SPCPIO

    .file       "spcpio.S"

    .text
    .arm                        @ This is ARM code; performs the same action as .code 32
    .align      2               @ Align to word boundary; "2" means the number of bits that must be zero
    .globl      gpio_pio_init
    .type       gpio_pio_init, %function

gpio_pio_init:
        /*
         * GPIO init
         */
        ldr     r0, =MARIA_REGBANK_BASE
        add     r0, r0, #RB_GPIO_0_CONFIG_OFFSET-4
        mov     r2, #0

        /* GPIO 0-7*/
        ldr r1, [r10, #NVRAM_GPIO_0_7_CFG_OFFSET]          /* r1 = gpio_0_7_cfg; loaded from NVRAM */
.Lgpio07:
        lsr     r3, r1, r2                                 /* r3 = r1 >> r2 */
        and     r3, r3, #NVRAM_GPIO_MASK                   /* r3 = gpio_x   */
        str     r3, [r0, #4]!                              /* r4 -> r0 + 4 and after r0 += 4 */
        add     r2, r2, #NVRAM_GPIO_SHIFT                  /* r2 += 4 */
        cmp     r2, #(NVRAM_GPIO_7_SHIFT+NVRAM_GPIO_SHIFT) /* check if we wrote all 8 gpio fields */
        blt     .Lgpio07

        /* GPIO 8-15*/
        ldr r1, [r10, #NVRAM_GPIO_8_15_CFG_OFFSET]         /* r1 = gpio_8_15_cfg; loaded from NVRAM */
        mov     r2, #0
.Lgpio815:
        lsr     r3, r1, r2                                 /* r3 = r1 >> r2 */
        and     r3, r3, #NVRAM_GPIO_MASK                   /* r3 = gpio_x   */
        str     r3, [r0, #4]!                              /* r3 -> r0 + 4 and after r0 += 4 */
        add     r2, r2, #NVRAM_GPIO_SHIFT                  /* r2 += 4 */
        cmp     r2, #(NVRAM_GPIO_7_SHIFT+NVRAM_GPIO_SHIFT) /* check if we wrote all 8 gpio fields */
        blt     .Lgpio815

        /*
         * PIO init
         */
        ldr     r0, =MARIA_REGBANK_BASE
        ldr r1, [r10, #NVRAM_PKG_CFG_OFFSET]               /* r1 = pkg_cfg; loaded from NVRAM */
        lsr     r1, r1, #NVRAM_PIO_SHIFT
        and     r1, #NVRAM_PIO_MASK                        /* r1 = pio */
        str     r1, [r0, #RB_PIO_CONFIG_OFFSET]
        ldr     r1, =0x01
        str     r1, [r0, #RB_PIO_ENABLE_OFFSET]

        mov pc, lr                                         /* back to my caller */

#endif /* CONFIG_CHIP_FEATURE_SPCPIO */