summaryrefslogtreecommitdiff
path: root/cleopatre/u-boot-1.1.6/cpu/spc300/spceth.S
blob: 6938afb0cb208fa2b2d8fcd3c2d01e9f3bc2653e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
/*
 * cpu/spc300/spceth.S
 *
 * Copyright (C) 2009 SPiDCOM Technologies
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>

#ifdef CONFIG_CHIP_FEATURE_SPCETH

#include <asm/hardware.h>
#include <asm/arch/nvram.h>

    .file       "spceth.S"

    .text
    .arm                        @ This is ARM code; performs the same action as .code 32
    .align      2               @ Align to word boundary; "2" means the number of bits that must be zero
    .globl      ethernet_config
    .type       ethernet_config, %function


/* WARNING : Assusme that for macros r0=MARIA_REGBANK_BASE and r1 is not used */
    .macro      cmdoff, offset
                ldr     r1, =CLK_CMD_OFF
                str     r1, [r0, #\offset]
    .endm

    .macro      cmdon, offset
                ldr     r1, =CLK_CMD_ON
                str     r1, [r0, #\offset]
    .endm

    .macro      setreg, offset, val
                ldr     r1, =\val
                str     r1, [r0, #\offset]
    .endm

    .macro      checkreg, offset, val
1:              ldr     r1, [r0, #\offset]
                cmp     r1, #\val
                bne     1b
    .endm

ethernet_config:
    ldr r0, =MARIA_REGBANK_BASE

    /*
     * Switch off all Ethernet clock commands
     */
    cmdoff RB_CLK_CMD_ETH_TX_125_OFFSET
    checkreg RB_CLK_STAT_ETH_TX_125_OFFSET, CLK_IS_OFF

    cmdoff RB_CLK_CMD_ETH_TX_EXT_OFFSET
    checkreg RB_CLK_STAT_ETH_TX_EXT_OFFSET, CLK_IS_OFF

    cmdoff RB_CLK_CMD_ETH_RX_EXT_OFFSET
    checkreg RB_CLK_STAT_ETH_RX_EXT_OFFSET, CLK_IS_OFF

    cmdoff RB_CLK_CMD_ETH_RMII_OFFSET
    checkreg RB_CLK_STAT_ETH_RMII_OFFSET, CLK_IS_OFF

    /*
     * Enable PHY Clock
     */
    /* release EXT reset for ETH PHY clock */
    ldr     r1, [r0, #RB_RST_MODULE_OFFSET]
    bic     r1, r1, #RST_EXT    /* clear bit 12 of RB_RST_MODULE, sw_rst_ext -> 0 */
    str     r1, [r0, #RB_RST_MODULE_OFFSET]
    /* Enable PHY Clock */
    cmdon RB_CLK_CMD_OUT25_OFFSET
    checkreg RB_CLK_STAT_OUT25_OFFSET, CLK_IS_ON


    /*
     * Find Ethernet Mode from NVRAM
     * we assume that r10 = NVRAM Base Address
     * default mode is GMII
     */
    ldr r3, [r10, #NVRAM_PKG_CFG_OFFSET]  /* find pkg_cfg */
    lsr r3, r3, #NVRAM_ETH1_MODE_SHIFT
    and r3, r3, #NVRAM_ETH1_MODE_MASK      /* r3 = eth_mode */
    cmp r3, #NVRAM_ETH_MODE_MII
    beq 10f                               /* eth_mode = MII */
    cmp r3, #NVRAM_ETH_MODE_RMII
    beq 20f                               /* eth_mode = RMII */

    /*
     * GMII mode
     */
    /* Ethernet Config for GMII mode */
    setreg RB_ETH_CONFIG_OFFSET, 0

    /* Enable TX 125MHz clock */
    setreg RB_CLK_SEL_ETH_MAC_OFFSET, CLK_SEL_ETH_MAC_125
    checkreg RB_CLK_SEL_STAT_ETH_MAC_OFFSET, CLK_SEL_ETH_MAC_125

    setreg RB_CLK_SEL_ETH_TX_OFFSET, CLK_SEL_ETH_TX_125
    checkreg RB_CLK_SEL_STAT_ETH_TX_OFFSET, CLK_SEL_ETH_TX_125

    cmdon RB_CLK_CMD_ETH_TX_125_OFFSET
    checkreg RB_CLK_STAT_ETH_TX_125_OFFSET, CLK_IS_ON

    /* Enable RX ext clock */
    setreg RB_CLK_SEL_ETH_RX_OFFSET, CLK_SEL_ETH_RX_EXT
    checkreg RB_CLK_SEL_STAT_ETH_RX_OFFSET, CLK_SEL_ETH_RX_EXT

    cmdon RB_CLK_CMD_ETH_RX_EXT_OFFSET
    checkreg RB_CLK_STAT_ETH_RX_EXT_OFFSET, CLK_IS_ON

    bal 100f

    /*
     * MII mode
     */
10:
    /* Ethernet Config for MII mode */
    setreg RB_ETH_CONFIG_OFFSET, 0

    /* Enable TX_ext clock */
    setreg RB_CLK_SEL_ETH_TX_OFFSET, CLK_SEL_ETH_TX_EXT
    checkreg RB_CLK_SEL_STAT_ETH_TX_OFFSET, CLK_SEL_ETH_TX_EXT

    cmdon RB_CLK_CMD_ETH_TX_EXT_OFFSET
    checkreg RB_CLK_STAT_ETH_TX_EXT_OFFSET, CLK_IS_ON

    /* Enable RX_ext clock */
    setreg RB_CLK_SEL_ETH_RX_OFFSET, CLK_SEL_ETH_RX_EXT
    checkreg RB_CLK_SEL_STAT_ETH_RX_OFFSET, CLK_SEL_ETH_RX_EXT

    cmdon RB_CLK_CMD_ETH_RX_EXT_OFFSET
    checkreg RB_CLK_STAT_ETH_RX_EXT_OFFSET, CLK_IS_ON

    bal 100f


    /*
     * RMII mode
     */
20:
    /* Ethernet Config for RMII mode */
    setreg RB_ETH_CONFIG_OFFSET, (ETH_CFG_RMII|ETH_CFG_RMII_100)

    /* Enable TX 25MHz clock */
    setreg RB_CLK_SEL_ETH_TX_OFFSET, CLK_SEL_ETH_TX_25
    checkreg RB_CLK_SEL_STAT_ETH_TX_OFFSET, CLK_SEL_ETH_TX_25
 
    /* Enable RX 25MHz clock */
    setreg RB_CLK_SEL_ETH_RX_OFFSET, CLK_SEL_ETH_RX_25
    checkreg RB_CLK_SEL_STAT_ETH_RX_OFFSET, CLK_SEL_ETH_RX_25

    /* Put RMII clock to 50MHz we assume that RMII is always 100Mbits */
    setreg RB_CLK_DIV_ETH_25_OFFSET, CLK_DIV_ETH_25_2
    checkreg RB_CLK_DIV_STAT_ETH_25_OFFSET, CLK_DIV_ETH_25_2

    setreg RB_CLK_SEL_ETH_MAC_OFFSET, CLK_SEL_ETH_MAC_RMII
    checkreg RB_CLK_SEL_STAT_ETH_MAC_OFFSET, CLK_SEL_ETH_MAC_RMII

    /* Enable RMII */
    cmdon RB_CLK_CMD_ETH_RMII_OFFSET
    checkreg RB_CLK_STAT_ETH_RMII_OFFSET, CLK_IS_ON


100:
    /* back to my caller */
    mov	pc, lr

#endif /* CONFIG_CHIP_FEATURE_SPCETH */