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path: root/cleopatre/u-boot-1.1.6/board/sdk300/sdk300.c
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/*
 * board/sdk300/sdk300.c
 *
 * Copyright (C) 2009 SPiDCOM Technologies
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/nvram.h>

extern void enable_mmu(void);

#if defined(CONFIG_SHOW_BOOT_PROGRESS)
void show_boot_progress(int progress)
{
	printf("Boot reached stage %d\n", progress);
}
#endif

/**
 * Function:     get_sdram_size
 * Parameters:   bd_t * bd
 * Purpose:      get RAM size from NVRAM
 * Return Value: ulong size
 */
ulong get_sdram_size(bd_t *bd)
{
    spidcom_nvram_t *nvram;
    /* We will access to NVRAM through SPI direct access */
    nvram = (spidcom_nvram_t *)(bd->bi_nvram_addr);
#if defined (CONFIG_CHIP_FEATURE_SDRAM_CTRL)
    ulong sconr;
    ulong row, col, bank, byte;

    sconr = nvram->dram.sdram.config;

    bank = 1 << ( ( (sconr & SCONR_s_bank_addr_width_RegisterMask) >> SCONR_s_bank_addr_width_BitAddressOffset) + 1);
    row  = 1 << ( ( (sconr & SCONR_s_row_addr_width_RegisterMask) >> SCONR_s_row_addr_width_BitAddressOffset) + 1);
    col  = 1 << ( ( (sconr & SCONR_s_col_addr_width_RegisterMask) >> SCONR_s_col_addr_width_BitAddressOffset) + 1);
    byte = ( ( 1<<( (sconr & SCONR_s_data_width_RegisterMask) >> SCONR_s_data_width_BitAddressOffset) ) * 2);

    return (bank * row * col * byte);
#elif defined (CONFIG_CHIP_FEATURE_MIU_CTRL)
    return nvram->dram.miu.ram_size;
#else
#   error "Unknown DRAM controller"
#endif
}

/**
 * Function:     set_eth_mac_addr
 * Parameters:   bd_t * bd
 * Purpose:      set MAC address from NVRAM to env
 * Return Value: void
 */
static void set_eth_mac_addr(bd_t *bd)
{
    spidcom_nvram_t *nvram = NULL;
    char nvram_eth[6];
    ulong eth_lsb, eth_msb;
    volatile ulong *mac_reg;
    char eth_str[18] = {0};     /* in the form 11:22:33:44:55:66, i.e. with ':' delimiters */

    /* We will access to NVRAM through SPI direct access */
    nvram = (spidcom_nvram_t *)(bd->bi_nvram_addr);

    /* SPI direct can access to flash only through 32bits */
    eth_lsb = *((uint32_t*)nvram->eth1_address);
    eth_msb = *(((uint32_t*)nvram->eth1_address)+1);
    eth_msb &= 0x0000FFFF;

    /* Put this MAC address directly in IP Registers */
    mac_reg = (volatile ulong*)(Register17);
    *mac_reg = eth_lsb;
    mac_reg = (volatile ulong*)(Register16);
    *mac_reg = eth_msb;

    /* Store this MAC address under env variable */
    nvram_eth[0] = (eth_lsb & 0x000000FF);
    nvram_eth[1] = (eth_lsb & 0x0000FF00)>>8;
    nvram_eth[2] = (eth_lsb & 0x00FF0000)>>16;
    nvram_eth[3] = (eth_lsb & 0xFF000000)>>24;
    nvram_eth[4] = (eth_msb & 0x000000FF);
    nvram_eth[5] = (eth_msb & 0x0000FF00)>>8;

    sprintf( eth_str, "%.2x:%.2x:%.2x:%.2x:%.2x:%.2x",
             nvram_eth[0], nvram_eth[1], nvram_eth[2],
             nvram_eth[3], nvram_eth[4], nvram_eth[5] );

    /* Now set env with it */
    setenv("ethaddr", eth_str);
}

/**
 * Function:     delay
 * Parameters:   unsigned long loops
 * Purpose:      wait delay
 * Return Value: void
 */
static inline void delay (unsigned long loops)
{
	__asm__ volatile ("1:\n"
		"subs %0, %1, #1\n"
		"bne 1b":"=r" (loops):"0" (loops));
} /* delay */

/*
 * Miscellaneous platform dependent initialisations
 */
/**
 * Function:     board_init
 * Parameters:   void
 * Purpose:      Initialize board
 * Return Value: int
 */
int board_init (void)
{
	DECLARE_GLOBAL_DATA_PTR;
    register volatile unsigned int nvram_addr asm ("r10");

    /* NVRAM address will be passed to C from assembly start-up in reg r10 */
    gd->bd->bi_nvram_addr = nvram_addr;

    /* arch number of SPiDCOM Board */
#ifdef CONFIG_CHIP_MSE500DINI_300
    gd->bd->bi_arch_number = MACH_TYPE_MSE500DINI_300;
#elif defined(CONFIG_CHIP_MSE500)
    gd->bd->bi_arch_number = MACH_TYPE_MSE500;
#else
    gd->bd->bi_arch_number = MACH_TYPE_SPC300;
#endif

	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

#ifdef CONFIG_CHIP_FEATURE_DINI_UART_SELECT
	/* Select UART. */
	writel(RB_DINI_UART_SELECT_ARM, RB_DINI_UART_SELECT);
#endif

#ifdef CONFIG_CHIP_FEATURE_SYNOP3504_PHY_RX_CLOCK_INVERT
	/* Invert RX Ethernet clock. */
	writel(readl (RB_DINI_SPARE_1)
	       | RB_DINI_SPARE_1_ETH_RX_CLOCK_INVERT,
	       RB_DINI_SPARE_1);
#endif

	/* Enable Ctrlc */
	console_init_f();

    /* Active MMU and Data Cache for better performances */
    enable_mmu();

	return 0;
} /* board_init */


int board_late_init(void)
{
	DECLARE_GLOBAL_DATA_PTR;
	spidcom_nvram_t *nvram = NULL;

        /* Now printf is allowed we can print an eventually NVRAM error */
        nvram = (spidcom_nvram_t *)(gd->bd->bi_nvram_addr);
        if((gd->bd->bi_nvram_addr & 0xFF000000) != PHYS_FLASH_SPI_1)
        {
            printf("No NVRAM Found\n");
            while(1);
        }

        /* Set Ethernet MAC Address */
        set_eth_mac_addr(gd->bd);

	return(0);
}


/**
 * Function:     dram_init
 * Parameters:   void
 * Purpose:      init dram
 * Return Value: int
 */
int dram_init (void)
{
	DECLARE_GLOBAL_DATA_PTR;

	gd->bd->bi_dram[0].start = PHYS_SDRAM;
	gd->bd->bi_dram[0].size = get_sdram_size(gd->bd);

	return 0;
} /* dram_init */