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#ifndef synop3504_reg_h
#define synop3504_reg_h
/* Cleopatre project {{{
 *
 * Copyright (C) 2008 SPiDCOM Technologies
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * }}} */
/**
 * \file    driver/net/arm/synop3504_reg.h
 * \brief   Register definition for Synopsys 3504 driver.
 * \ingroup cleopatre_net_driver.
 */

/** GMAC registers structure */
enum GmacRegisters
{
    GmacConfig         = 0x00,  //config
    GmacFrameFilter    = 0x04,  //frame filter
    GmacHashHigh       = 0x08,  //multi-cast hash table high
    GmacHashLow        = 0x0C,  //multi-cast hash table low
    GmacGmiiAddr       = 0x10,  //GMII address
    GmacGmiiData       = 0x14,  //GMII data
    GmacFlowControl    = 0x18,  //Flow control
    GmacVlan           = 0x1C,  //VLAN tag
    GmacVersion	       = 0x20,  //Version of Gmac

    GmacWakeupAddr     = 0x28,  //Wake-up frame filter adrress reg
    GmacPmtCtrlStatus  = 0x2C,  //PMT control and status register

    GmacIntStatus      = 0x38,  //Gmac interupt status
    GmacIntMask	       = 0x3C,  //Gmac interupt status
    GmacAddr0High      = 0x40,  //address0 high
    GmacAddr0Low       = 0x44,  //address0 low
    GmacAddr1High      = 0x48,  //address1 high
    GmacAddr1Low       = 0x4C,  //address1 low
    GmacAddr2High      = 0x50,  //address2 high
    GmacAddr2Low       = 0x54,  //address2 low
    GmacAddr3High      = 0x58,  //address3 high
    GmacAddr3Low       = 0x5C,  //address3 low
    GmacAddr4High      = 0x60,  //address4 high
    GmacAddr4Low       = 0x64,  //address4 low
    GmacAddr5High      = 0x68,  //address5 high
    GmacAddr5Low       = 0x6C,  //address5 low
    GmacAddr6High      = 0x70,  //address6 high
    GmacAddr6Low       = 0x74,  //address6 low
    GmacAddr7High      = 0x78,  //address7 high
    GmacAddr7Low       = 0x7C,  //address7 low
    GmacAddr8High      = 0x80,  //address8 high
    GmacAddr8Low       = 0x84,  //address8 low
    GmacAddr9High      = 0x88,  //address9 high
    GmacAddr9Low       = 0x8C,  //address9 low
    GmacAddr10High     = 0x90,  //address10 high
    GmacAddr10Low      = 0x94,  //address10 low
    GmacAddr11High     = 0x98,  //address11 high
    GmacAddr11Low      = 0x9C,  //address11 low
    GmacAddr12High     = 0xA0,  //address12 high
    GmacAddr12Low      = 0xA4,  //address12 low
    GmacAddr13High     = 0xA8,  //address13 high
    GmacAddr13Low      = 0xAC,  //address13 low
    GmacAddr14High     = 0xB0,  //address14 high
    GmacAddr14Low      = 0xB4,  //address14 low
    GmacAddr15High     = 0xB8,  //address15 high
    GmacAddr15Low      = 0xBC,  //address15 low
    // AN registers
    GmacANControl      = 0xC0,  //AN Control
    GmacANStatus       = 0xC4,  //AN Status
    GmacANAdwert       = 0xC8,  //AN Advertisement
    GmacANLPA          = 0xCC,  //AN Link Partner Ability
    GmacANExpansion    = 0xD0,  //AN Expansion
    GmacTBIExStatus    = 0xD4,  //TBI Extended Status

    //MMC registers
    MmcCntrl             = 0x0100, //MMC Control
    MmcIntrRx            = 0x0104, //MMC Receive
    MmcIntrTx            = 0x0108, //MMC Transmit Interrupt
    MmcIntrMaskRx        = 0x010C, //MMC Receive Interrupt Mask
    MmcIntrMaskTx        = 0x0110, //MMC Transmit Interrupt Mask
    TxOctetCountGb       = 0x0114, //Nb bytes transmitted
    TxFrameCountGb       = 0x0118, //Nb good and bad frames transmitted
    TxBroadcastFramesG   = 0x011C, //Nb good broadcast frames transmitted
    TxMulticastFramesG   = 0x0120, //Nb good multicast frames transmitted
    Tx64OctetsGb         = 0x0124, //Nb good and bad frames transmitted with length 64 bytes
    Tx65To127OctetsGb    = 0x0128, //Nb good and bad frames transmitted with length between 65 and 127 bytes
    Tx128To255OctetsGb   = 0x012C, //Nb good and bad frames transmitted with length between 128 and 255 bytes
    Tx256To511OctetsGb   = 0x0130, //Nb good and bad frames transmitted with length between 256 and 511 bytes
    Tx512To1023OctetsGb  = 0x0134, //Nb good and bad frames transmitted with length between 512 and 1023 bytes
    Tx1024ToMaxOctetsGb  = 0x0138, //Nb good and bad frames transmitted with length between 1024 and maxsize bytes
    TxUnicastFramesGb    = 0x013C, //Nb good and bad unicast frames transmitted
    TxMulticastFramesGb  = 0x0140, //Nb good and bad multicast frames transmitted
    TxBroadcastFramesGb  = 0x0144, //Nb good and bad broadcast frames transmitted
    TxUnderflowError     = 0x0148, //Nb frames aborted due to frame underflow error
    TxSingleColG         = 0x014C, //Nb successfully transmitted frames after a single collision in Half-duplex mode
    TxMultiColG          = 0x0150, //Nb successfully transmitted frames after more than a single collision in Half-duplex mode
    TxDeferred           = 0x0154, //Nb successfully transmitted frames after a deferral in Halfduplex mode
    TxLateCol            = 0x0158, //Nb frames aborted due to late collision error
    TxExessCol           = 0x015C, //Nb frames aborted due to excessive (16) collision errors
    TxCarrierError       = 0x0160, //Nb frames aborted due to carrier sense error
    TxOctetCountG        = 0x0164, //Nb bytes transmitted, exclusive of preamble
    TxFrameCountG        = 0x0168, //Nb good frames transmitted
    TxExcessDef          = 0x016C, //Nb frames aborted due to excessive deferral error
    TxPauseFrames        = 0x0170, //Nb good PAUSE frames transmitted
    TxVlanFramesG        = 0x0174, //Nb good VLAN frames transmitted
    RxFrameCountGb       = 0x0180, //Nb good and bad frames received
    RxOctetCountGb       = 0x0184, //Nb bytes received, exclusive of preamble, in good and bad frames
    RxOctetCountG        = 0x0188, //Nb bytes received, exclusive of preamble, only in good frames
    RxBroadcastFramesG   = 0x018C, //Nb good broadcast frames received
    RxMulticastFramesG   = 0x0190, //Nb good multicast frames received
    RxCrcError           = 0x0194, //Nb frames received with CRC error
    RxAlignmentError     = 0x0198, //Nb frames received with alignment (dribble) error. Valid only in 10/100 mode
    RxRuntError          = 0x019C, //Nb frames received with runt (<64 bytes and CRC error) error
    RxJabberError        = 0x01A0, //Nb giant frames received with length greater than 1518 bytes and with CRC error
    RxUnderSizeG         = 0x01A4, //Nb frames received with length less than 64 bytes, without any errors
    RxOverSizeG          = 0x01A8, //Nb frames received with length greater than the maxsize without errors
    Rx64OctetsGb         = 0x01AC, //Nb good and bad frames received with length 64 bytes, exclusive of preamble
    Rx65To127OctetsGb    = 0x01B0, //Nb good and bad frames received with length between 65 and 127bytes, exclusive of preamble
    Rx128To255OctetsGb   = 0x01B4, //Nb good and bad frames received with length between 128 and 255 bytes, exclusive of preamble
    Rx256To511OctetsGb   = 0x01B8, //Nb good and bad frames received with length between 256 and 511 bytes, exclusive of preamble
    Rx512To1023OctetsGb  = 0x01BC, //Nb good and bad frames received with length between 512 and 1023 bytes, exclusive of preamble
    Rx1024ToMaxOctetsGb  = 0x01C0, //Nb good and bad frames received with length between 1024 and maxsize bytes, exclusive of preamble and retried frames
    RxUnicastFramesG     = 0x01C4, //Nb good unicast frames received
    RxLengthError        = 0x01C8, //Nb frames received with length error, for all frames with valid length field
    RxOutOfRangeType     = 0x01CC, //Nb frames received with length field not equal to the valid frame size
    RxPauseFrames        = 0x01D0, //Nb good and valid PAUSE frames received
    RxFifoOverflow       = 0x01D4, //Nb missed received frames due to FIFO overflow
    RxVlanFramesGb       = 0x01D8, //Nb good and bad VLAN frames received
    RxWatchDogError      = 0x01DC, //Nb frames received with error due to watchdog timeout error
    MmcIpcIntrMaskRx     = 0x0200, //MMC IPC Receive Checksum Offload Interrupt Mask
    MmcIpcIntrRx         = 0x0208, //MMC Receive Checksum Offload Interrupt
    RxIpv4GdFrms         = 0x0210, //Nb good IPv4 datagrams received with the TCP, UDP, or ICMP payload
    RxIpv4HdrErrFrms     = 0x0214, //Nb IPv4 datagrams received with header errors
    RxIpv4NopayFrms      = 0x0218, //Nb IPv4 datagram frames received that did not have a TCP, UDP, or ICMP payload processed by the Checksum engine
    RxIpv4FragFrms       = 0x021C, //Nb good IPv4 datagrams with fragmentation
    RxIpv4UdsblFrms      = 0x0220, //Nb good IPv4 datagrams received that had a UDP payload with checksum disabled
    RxIpv6GdFrms         = 0x0224, //Nb good IPv6 datagrams received with TCP, UDP, or ICMP payloads
    RxIpv6HdrErrFrms     = 0x0228, //Nb IPv6 datagrams received with header errors
    RxIpv6NoPayFrms      = 0x022C, //Nb IPv6 datagram frames received that did not have a TCP, UDP, or ICMP payload
    RxUdpGdFrms          = 0x0230, //Nb good IP datagrams with a good UDP payload
    RxUdpErrFrms         = 0x0234, //Nb good IP datagrams whose UDP payload has a checksum error
    RxTcpGdFrms          = 0x0238, //Nb good IP datagrams with a good TCP payload
    RxTcpErrFrms         = 0x023C, //Nb good IP datagrams whose TCP payload has a checksum error
    RxIcmpGdFrms         = 0x0240, //Nb good IP datagrams with a good ICMP payload
    RxIcmpErrFrms        = 0x0244, //Nb good IP datagrams whose ICMP payload has a checksum error
    RxIpv4GdOctets       = 0x0250, //Nb bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data
    RxIpv4HdrErrOctets   = 0x0254, //Nb bytes received in IPv4 datagrams with header errors
    RxIpv4NoPayOctets    = 0x0258, //Nb bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload
    RxIpv4FragOctets     = 0x025C, //Nb bytes received in fragmented IPv4 datagrams
    RxIpv4UdsblOctets    = 0x0260, //Nb bytes received in a UDP segment that had the UDP checksum disabled
    RxIpv6GdOctets       = 0x0264, //Nb bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6 data
    RxIpv6HdrErrOctets   = 0x0268, //Nb bytes received in IPv6 datagrams with header errors
    RxIpv6NoPayOctets    = 0x026C, //Nb bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload
    RxUdpGdOctets        = 0x0270, //Nb bytes received in a good UDP segment
    RxUdpErrOctets       = 0x0274, //Nb bytes received in a UDP segment that had checksum errors
    RxTcpGdOctets        = 0x0278, //Nb bytes received in a good TCP segment
    RxTcpErrOctets       = 0x027C, //Nb bytes received in a TCP segment with checksum errors
    RxIcmpGdOctets       = 0x0280, //Nb bytes received in a good ICMP segment
    RxIcmpErrOctets      = 0x0284, //Nb bytes received in an ICMP segment with checksum errors
};

/** DMA registers structure */
enum DmaRegisters
{
    DmaBusMode        = 0x00,  //CSR0 - Bus Mode
    DmaTxPollDemand   = 0x04,  //CSR1 - Transmit Poll Demand
    DmaRxPollDemand   = 0x08,  //CSR2 - Receive Poll Demand
    DmaRxBaseAddr     = 0x0C,  //CSR3 - Receive list base address
    DmaTxBaseAddr     = 0x10,  //CSR4 - Transmit list base address
    DmaStatus         = 0x14,  //CSR5 - Dma status
    DmaControl        = 0x18,  //CSR6 - Dma control
    DmaInterrupt      = 0x1C,  //CSR7 - Interrupt enable
    DmaMissedFr       = 0x20,  //CSR8 - Missed Frame Counter

    DmaTxCurrDesc     = 0x48,  //CSR20 - Current host transmit buffer address
    DmaRxCurrDesc     = 0x4C,  //CSR20 - Current host receive buffer address
    DmaTxCurrBuff     = 0x50,  //CSR21 - Current host transmit buffer address
    DmaRxCurrBuff     = 0x54,  //CSR21 - Current host receive buffer address
};

/** GmacConfig registers field */
enum GmacConfigReg
{
    GmacWatchdogDisable      = 0x00800000,  //Disable watchdog timer on Rx
    GmacWatchdogEnable       = 0x00000000,  //Enable watchdog timer

    GmacJabberDisable        = 0x00400000,  //Disable jabber timer on Tx
    GmacJabberEnable         = 0x00000000,  //Enable jabber timer

    GmacFrameBurstEnable     = 0x00200000,  //Enable frame bursting during Tx
    GmacFrameBurstDisable    = 0x00000000,  //Disable frame bursting

    GmacJumboFrameEnable     = 0x00100000,  //Enable jumbo frame for Tx
    GmacJumboFrameDisable    = 0x00000000,  //Disable jumbo frame

    GmacInterFrameGap7       = 0x000E0000,  //Config7 - 40 bit times
    GmacInterFrameGap6       = 0x000C0000,  //Config6 - 48 bit times
    GmacInterFrameGap5       = 0x000A0000,  //Config5 - 56 bit times
    GmacInterFrameGap4       = 0x00080000,  //Config4 - 64 bit times
    GmacInterFrameGap3       = 0x00040000,  //Config3 - 72 bit times
    GmacInterFrameGap2       = 0x00020000,  //Config2 - 80 bit times
    GmacInterFrameGap1       = 0x00010000,  //Config1 - 88 bit times
    GmacInterFrameGap0       = 0x00000000,  //Config0 - 96 bit times

    GmacDisableCrs	   = 0x00010000,
    GmacMiiGmii		   = 0x00008000,
    GmacSelectMii            = 0x00008000,  //Port Select-MII mode
    GmacSelectGmii           = 0x00000000,  //GMII mode

    GmacFESpeed100           = 0x00004000,  //Fast Ethernet speed 100Mbps
    GmacFESpeed10            = 0x00000000,  //10Mbps

    GmacDisableRxOwn         = 0x00002000,  //Disable receive own packets
    GmacEnableRxOwn          = 0x00000000,  //Enable receive own packets

    GmacLoopbackOn           = 0x00001000,  //Loopback mode for GMII/MII
    GmacLoopbackOff          = 0x00000000,  //Normal mode

    GmacFullDuplex           = 0x00000800,  //Full duplex mode
    GmacHalfDuplex           = 0x00000000,  //Half duplex mode

    GmacRxIpcOffload	   = 0x00000400,  //IPC checksum offload

    GmacRetryDisable         = 0x00000200,  //Disable Retry
    GmacRetryEnable          = 0x00000000,  //Enable retransmission as per BL

    GmacLinkUp               = 0x00000100,  //Link UP
    GmacLinkDown             = 0x00000100,  //Link Down

    GmacPadCrcStripEnable    = 0x00000080,  //Automatic Pad/Crc strip enable
    GmacPadCrcStripDisable   = 0x00000000,  //Automatic Pad/Crc stripping disable

    GmacBackoffLimit3        = 0x00000060,  //Back-off limit in HD mode
    GmacBackoffLimit2        = 0x00000040,
    GmacBackoffLimit1        = 0x00000020,
    GmacBackoffLimit0        = 0x00000000,

    GmacDeferralCheckEnable  = 0x00000010,  //Deferral check enable in HD mode
    GmacDeferralCheckDisable = 0x00000000,  //Deferral check disable

    GmacTxEnable             = 0x00000008,  //Transmitter enable
    GmacTxDisable            = 0x00000000,  //Transmitter disable

    GmacRxEnable             = 0x00000004,  //Receiver enable
    GmacRxDisable            = 0x00000000,  //Receiver disable
};

/** GmacFrameFilter registers field */
enum GmacFrameFilterReg
{
    GmacFilterMask	     = 0x80000000,
    GmacFilterOff            = 0x80000000,  //Receive all incoming packets
    GmacFilterOn             = 0x00000000,  //Receive filtered packets only

    GmacHashPerfectFilter    = 0x00000400,  //Hash or Perfect Filter enable

    GmacSrcAddrFilterMask    = 0x00000200,
    GmacSrcAddrFilterEnable  = 0x00000200,  //Source Address Filter enable
    GmacSrcAddrFilterDisable = 0x00000000,

    GmacSrcInvaAddrFilterMask= 0x00000100,
    GmacSrcInvAddrFilterEn   = 0x00000100,  //Inv Src Addr Filter enable
    GmacSrcInvAddrFilterDis  = 0x00000000,

    GmacPassControlMask	     = 0x000000C0,
    GmacPassControl3         = 0x000000C0,  //Forwards ctrl frms that pass AF
    GmacPassControl2         = 0x00000080,  //Forwards all control frames
    GmacPassControl1         = 0x00000040,  //Does not pass control frames
    GmacPassControl0         = 0x00000000,  //Does not pass control frames

    GmacBroadcastMask        = 0x00000020,
    GmacBroadcastDisable     = 0x00000020,  //Disable Rx of broadcast frames
    GmacBroadcastEnable      = 0x00000000,  //Enable broadcast frames

    GmacMulticastFilterMask  = 0x00000010,
    GmacMulticastFilterOff   = 0x00000010,  //Pass all multicast packets
    GmacMulticastFilterOn    = 0x00000000,  //Pass filtered multicast packets

    GmacDestAddrFilterMask   = 0x00000008,
    GmacDestAddrFilterInv    = 0x00000008,  //Inverse filtering for DA
    GmacDestAddrFilterNor    = 0x00000000,  //Normal filtering for DA

    GmacMcastHashFilterMask  = 0x00000004,
    GmacMcastHashFilterOn    = 0x00000004,  //perfom multicast hash filtering
    GmacMcastHashFilterOff   = 0x00000000,  //perfect filtering only

    GmacUcastHashFilterMask  = 0x00000002,
    GmacUcastHashFilterOn    = 0x00000002,  //Unicast Hash filtering only
    GmacUcastHashFilterOff   = 0x00000000,  //perfect filtering only

    GmacPromiscuousModeMask  = 0x00000001,
    GmacPromiscuousModeOn    = 0x00000001,  //Receive all frames
    GmacPromiscuousModeOff   = 0x00000000,  //Receive filtered packets only
};

/** GmacFlowControl registers field */
enum  GmacFlowControlReg
{
    GmacFlowCtrlTimePauseShift=16,
    GmacFlowCtrlTimePauseMask= 0xFFFF0000,  //Pause time for transit control frames
    GmacFlowCtrlDisZQuanta   = 0x00000080,  //Disable automatic Zero-Quanta pause control frame generation
    GmacFlowCtrlThresh256    = 0x00000030,  //Pause time minus 256 slot times
    GmacFlowCtrlThresh144    = 0x00000020,  //Pause time minus 144 slot times
    GmacFlowCtrlThresh28     = 0x00000010,  //Pause time minus 28 slot times
    GmacFlowCtrlThresh4      = 0x00000000,  //Pause time minus 4 slot times
    GmacFlowCtrlUnicast      = 0x00000008,  //Enable Flow Control on Unicast frames
    GmacFlowCtrlRxEn         = 0x00000004,  //Enable Rx Flow Control
    GmacFlowCtrlTxEn         = 0x00000002,  //Enable Tx Flow Control
    GmacFlowCtrlBackPress    = 0x00000001,  //Activate back-pressure
};

/** GmacGmiiAddr registers field */
enum GmacGmiiAddrReg
{
    GmiiDevMask       = 0x0000F800,  //GMII device address
    GmiiDevShift      = 11,
    GmiiRegMask       = 0x000007C0,  //GMII register in selected Phy
    GmiiRegShift      = 6,

    GmiiCsrClkMask    = 0x0000001C,  //CSR Clock bit Mask
    GmiiCsrClk5       = 0x00000014,  //CSR Clock Range 250-300 MHz
    GmiiCsrClk4       = 0x00000010,  //                150-250 MHz
    GmiiCsrClk3       = 0x0000000C,  //                 35-60  MHz
    GmiiCsrClk2       = 0x00000008,  //                 20-35  MHz
    GmiiCsrClk1       = 0x00000004,  //                100-150 MHz
    GmiiCsrClk0       = 0x00000000,  //                 60-100 MHz

    GmiiWrite         = 0x00000002,  //Write to register
    GmiiRead          = 0x00000000,  //Read from register

    GmiiBusy          = 0x00000001,  //GMII interface is busy
};

/** GmacGmiiData registers field */
enum GmacGmiiDataReg
{
    GmiiDataMask      = 0x0000FFFF,  //GMII Data
};

/** DmaBusMode registers field */
enum DmaBusModeReg
{
    DmaSeparatePBLEnable = 0x00800000,  //Use a separate Burst Length for TX and RX
    DmaSeparatePBLDisable= 0x00000000,

    DmaRxBurstLength32   = 0x00400000,  //Programmable DMA RX burst length = 32
    DmaRxBurstLength16   = 0x00200000,  //RX burst length = 16
    DmaRxBurstLength8    = 0x00100000,  //RX burst length = 8
    DmaRxBurstLength4    = 0x00080000,  //RX burst length = 4
    DmaRxBurstLength2    = 0x00040000,  //RX burst length = 2
    DmaRxBurstLength1    = 0x00020000,  //RX burst length = 1

    DmaFixedBurstEnable  = 0x00010000,  //Fixed Burst SINGLE, INCR4, INCR8 or INCR16
    DmaFixedBurstDisable = 0x00000000,  //            SINGLE, INCR

    DmaTxPriorityRatio11 = 0x00000000,  //TX:RX DMA priority ratio 1:1
    DmaTxPriorityRatio21 = 0x00004000,  //TX:RX DMA priority ratio 2:1
    DmaTxPriorityRatio31 = 0x00008000,  //TX:RX DMA priority ratio 3:1
    DmaTxPriorityRatio41 = 0x0000C000,  //TX:RX DMA priority ratio 4:1

    DmaBurstLength32     = 0x00002000,  //Programmable DMA burst length = 32
    DmaBurstLength16     = 0x00001000,  //DMA burst length = 16
    DmaBurstLength8      = 0x00000800,  //DMA burst length = 8
    DmaBurstLength4      = 0x00000400,  //DMA burst length = 4
    DmaBurstLength2      = 0x00000200,  //DMA burst length = 2
    DmaBurstLength1      = 0x00000100,  //DMA burst length = 1
    DmaBurstLength0      = 0x00000000,  //DMA burst length = 0

    DmaDescriptorSkip16  = 0x00000040,  //Descriptor skip length (no.of dwords)
    DmaDescriptorSkip8   = 0x00000020,  //between two unchained descriptors
    DmaDescriptorSkip4   = 0x00000010,
    DmaDescriptorSkip2   = 0x00000008,
    DmaDescriptorSkip1   = 0x00000004,
    DmaDescriptorSkip0   = 0x00000000,

    DmaArbitRr           = 0x00000000,  //DMA RR arbitration
    DmaArbitPr           = 0x00000002,  //Rx has priority over Tx

    DmaResetOn           = 0x00000001,  //Software Reset DMA engine
    DmaResetOff          = 0x00000000,
};

/** DmaControl registers field */
enum DmaControlReg
{
    DmaDisableDropTcpCs	    = 0x04000000,  //Dis. drop. of tcp/ip CS error frames

    DmaStoreAndForwardRx    = 0x02000000,  //Store and forward for Rx
    DmaStoreAndForwardTx    = 0x00200000,  //Store and forward for Tx
    DmaFlushTxFifo          = 0x00100000,  //Tx FIFO controller is reset to default

    DmaTxThreshCtrl         = 0x0001C000,  //Controls thre Threh of MTL tx Fifo
    DmaTxThreshCtrl16       = 0x0001C000,  //Controls thre Threh of MTL tx Fifo 16
    DmaTxThreshCtrl24       = 0x00018000,  //Controls thre Threh of MTL tx Fifo 24
    DmaTxThreshCtrl32       = 0x00014000,  //Controls thre Threh of MTL tx Fifo 32
    DmaTxThreshCtrl40       = 0x00010000,  //Controls thre Threh of MTL tx Fifo 40
    DmaTxThreshCtrl256      = 0x0000c000,  //Controls thre Threh of MTL tx Fifo 256
    DmaTxThreshCtrl192      = 0x00008000,  //Controls thre Threh of MTL tx Fifo 192
    DmaTxThreshCtrl128      = 0x00004000,  //Controls thre Threh of MTL tx Fifo 128
    DmaTxThreshCtrl64       = 0x00000000,  //Controls thre Threh of MTL tx Fifo 64

    DmaTxStart              = 0x00002000,  //Start/Stop transmission

    DmaRxFlowCtrlDeact      = 0x00001800,  //Rx flow control deact. threhold
    DmaRxFlowCtrlDeact1K    = 0x00000000,  //Rx flow control deact. threhold (1kbytes)
    DmaRxFlowCtrlDeact2K    = 0x00000800,  //Rx flow control deact. threhold (2kbytes)
    DmaRxFlowCtrlDeact3K    = 0x00001000,  //Rx flow control deact. threhold (3kbytes)
    DmaRxFlowCtrlDeact4K    = 0x00001800,  //Rx flow control deact. threhold (4kbytes)

    DmaRxFlowCtrlAct        = 0x00000600,  //Rx flow control Act. threshold
    DmaRxFlowCtrlAct1K      = 0x00000000,  //Rx flow control Act. threshold (full - 1KB)
    DmaRxFlowCtrlAct2K      = 0x00000200,  //Rx flow control Act. threshold (full - 2KB)
    DmaRxFlowCtrlAct3K      = 0x00000400,  //Rx flow control Act. threshold (full - 3KB)
    DmaRxFlowCtrlAct4K      = 0x00000600,  //Rx flow control Act. threshold (full - 4KB)

    DmaEnHwFlowCtrl         = 0x00000100,  //Enable HW flow control
    DmaDisHwFlowCtrl        = 0x00000000,  //Disable HW flow control

    DmaFwdErrorFrames       = 0x00000080,  //Forward error frames
    DmaFwdUnderSzFrames     = 0x00000040,  //Forward undersize frames

    DmaRxThreshCtrl         = 0x00000018,  //Controls thre Threh of MTL rx Fifo
    DmaRxThreshCtrl128      = 0x00000018,  //Controls thre Threh of MTL rx Fifo 128
    DmaRxThreshCtrl96       = 0x00000010,  //Controls thre Threh of MTL rx Fifo 96
    DmaRxThreshCtrl32       = 0x00000008,  //Controls thre Threh of MTL rx Fifo 32
    DmaRxThreshCtrl64       = 0x00000000,  //Controls thre Threh of MTL rx Fifo 64

    DmaTxSecondFrame        = 0x00000004,  //Operate on second frame
    DmaRxStart              = 0x00000002,  //Start/Stop reception
};

/** DmaInterrupt registers field */
enum  DmaInterruptReg
{
  DmaIeNormal       = 0x00010000,  //Normal interrupt enable
  DmaIeAbnormal     = 0x00008000,  //Abnormal interrupt enable

  DmaIeEarlyRx      = 0x00004000,  //Early receive interrupt enable
  DmaIeBusError     = 0x00002000,  //Fatal bus error enable
  DmaIeEarlyTx      = 0x00000400,  //Early transmit interrupt enable
  DmaIeRxWdogTO     = 0x00000200,  //Receive Watchdog Timeout enable
  DmaIeRxStopped    = 0x00000100,  //Receive process stopped enable
  DmaIeRxNoBuffer   = 0x00000080,  //Receive buffer unavailable enable
  DmaIeRxCompleted  = 0x00000040,  //Completion of frame reception enable
  DmaIeTxUnderflow  = 0x00000020,  //Transmit underflow enable

  DmaIeRxOverflow   = 0x00000010,  //Receive Buffer overflow interrupt
  DmaIeTxJabberTO   = 0x00000008,  //Transmit Jabber Timeout enable
  DmaIeTxNoBuffer   = 0x00000004,  //Transmit buffer unavailable enable
  DmaIeTxStopped    = 0x00000002,  //Transmit process stopped enable
  DmaIeTxCompleted  = 0x00000001,  //Transmit completed enable
};

#endif /* synop3504_reg_h */