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path: root/cesar/hal/phy/src/phy.c
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/* Cesar project {{{
 *
 * Copyright (C) 2008 Spidcom
 *
 * <<<Licence>>>
 *
 * }}} */
/**
 * \file    hal/phy/src/phy.c
 * \brief   HAL Phy general functions.
 * \ingroup hal_phy
 */
#include "common/std.h"

#include "hal/phy/phy.h"

#include "inc/context.h"
#include "inc/regs.h"
#include "inc/resys.h"

#include "hal/leon/itc2.h"

#include "hal/arch/arch.h"

/** Interesting interrupts for the PHY. */
#define PHY_ITC2_MASK (BITS_MASK (1, LEON_ITC2_IT__RESYS) \
                       | BITS_MASK (1, LEON_ITC2_IT__PRATIC_ACCESS_CONF) \
                       | BITS_MASK (1, LEON_ITC2_IT__PRATIC_ACCESS) \
                       | BITS_MASK (1, LEON_ITC2_IT__PRATIC_INTERRUPT) \
                       | BITS_MASK (1, LEON_ITC2_IT__PB_DMA_END) \
                       | BITS_MASK (1, LEON_ITC2_IT__PB_DMA_ERROR))

/** TM DMA descriptor. */
struct phy_tmdma_desc_t
{
    /** Pointer to next descriptor. */
    struct phy_tmdma_desc_t *next;
    /** Pointer to data. */
    u32 *data;
    BITFIELDS_WORD (
    /** Transfer configuration: size. */
    u32 size_words:8;,
    /** Transfer configuration: memory index. */
    u32 mem_index:3;,
    /** Transfer configuration: last. */
    u32 last:1;,
    u32 :4;,
    /** Transfer configuration: local start address in memory. */
    u32 local_start_addr:16;)
};
typedef struct phy_tmdma_desc_t phy_tmdma_desc_t;

/** TM DMA memory indexes. */
enum phy_tmdma_mem_index_t
{
    PHY_TMDMA_MEM_TONEMASK = 0,
    PHY_TMDMA_MEM_AMPLITUDE_MAP = 1,
    PHY_TMDMA_MEM_ADAPT_TABLE = 2,
    PHY_TMDMA_MEM_TONEMAP_0 = 3,
    PHY_TMDMA_MEM_TONEMAP_1 = 4,
};

/** Global Phy context. */
static phy_t phy_global;

/**
 * Interrupt handler.
 * \param  vector  interrupt vector number
 * \param  data  phy context
 * \return  status
 */
static cyg_uint32
phy_isr (cyg_vector_t vector, cyg_addrword_t data)
{
    phy_t *ctx = (phy_t *) data;
    dbg_assert (ctx);
    bool call_dsr;
    dbg_assert (BF_GET (LEON_ITC2_STATUS_HIGH__IP, LEON_ITC2_STATUS_HIGH));
    uint it = BF_GET (LEON_ITC2_STATUS_HIGH__IRL, LEON_ITC2_STATUS_HIGH);
    if (it == LEON_ITC2_IT__RESYS)
    {
        u32 rx_date = PHY_PRATIC_STA_LAST_RECEIVED_FRAME_DATE
            - BF_GET (PHY_DSPSS_RESYS_DETECT_OFFSET__PREAMBLE,
                      PHY_DSPSS_RESYS_DETECT_OFFSET);
        bool fc_ok = (PHY_DSPSS_RX_FC_AV_STATUS &
                      PHY_DSPSS_RX_FC_AV_STATUS__OK_MASK)
            == PHY_DSPSS_RX_FC_AV_STATUS__OK_MASK;
        PHY_TRACE (RX_FC_CB, phy_date (ctx), rx_date);
        if (fc_ok)
        {
            u32 fc_av[4];
            fc_av[0] = PHY_DSPSS_RX_FC_AV_0;
            fc_av[1] = PHY_DSPSS_RX_FC_AV_1;
            fc_av[2] = PHY_DSPSS_RX_FC_AV_2;
            fc_av[3] = PHY_DSPSS_RX_FC_AV_3;
            call_dsr = ctx->rx_fc_cb (ctx->user_data, rx_date, fc_av);
        }
        else
            call_dsr = ctx->rx_fc_cb (ctx->user_data, rx_date, NULL);
    }
    else if (it == LEON_ITC2_IT__PB_DMA_END
             || it == LEON_ITC2_IT__PB_DMA_ERROR)
    {
        u32 status_word = PHY_PBDMA_STATUS_ERROR;
        PHY_TRACE (PBDMA_CB, phy_date (ctx), status_word);
        call_dsr = ctx->pbdma_cb (ctx->user_data, status_word);
    }
    else if (it == LEON_ITC2_IT__PRATIC_ACCESS)
    {
        PHY_TRACE (ACCESS_CB, phy_date (ctx));
        call_dsr = ctx->access_cb (ctx->user_data);
    }
    else if (it == LEON_ITC2_IT__PRATIC_ACCESS_CONF)
    {
        PHY_TRACE (ACCESS_CONF_CB, phy_date (ctx),
                   PHY_PRATIC_TIMER_2_EFFECTIVE_DATE);
        call_dsr = ctx->access_conf_cb (ctx->user_data);
    }
    else if (it == LEON_ITC2_IT__PRATIC_INTERRUPT)
    {
        PHY_TRACE (EXTRA_TIMER_CB, phy_date (ctx),
                   PHY_PRATIC_TIMER_5_EFFECTIVE_DATE);
        call_dsr = ctx->extra_timer_cb (ctx->user_data);
    }
    else
    {
        dbg_assert_default ();
    }
    LEON_ITC2_CLEAR = 1 << it;
    LEON_ITC1_CLEAR = 1 << LEON_ITC2_HIGH_PRIORITY_ITC1_IT;
    return (call_dsr ? CYG_ISR_CALL_DSR : 0) | CYG_ISR_HANDLED;
}

/**
 * DSR handler.
 * \param  vector  interrupt vector number
 * \param  count  number of time DSR was requested
 * \param  data  phy context
 * \return  status
 */
static void
phy_dsr (cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
    phy_t *ctx = (phy_t *) data;
    dbg_assert (ctx);
    PHY_TRACE (DEFERRED_CB, phy_date (ctx));
    ctx->deferred_cb (ctx->user_data);
}

phy_t *
phy_init (void *user_data, phy_rx_fc_cb_t rx_fc_cb, phy_access_cb_t access_cb,
          phy_access_conf_cb_t access_conf_cb, phy_pbdma_cb_t pbdma_cb,
          phy_tx_false_alarm_cb_t tx_false_alarm_cb,
          phy_deferred_cb_t deferred_cb)
{
    /* Initialise context. */
    phy_t *ctx = &phy_global;
    phy_trace_init (ctx);
    PHY_TRACE (INIT);
    ctx->user_data = user_data;
    ctx->rx_fc_cb = rx_fc_cb;
    ctx->access_cb = access_cb;
    ctx->access_conf_cb = access_conf_cb;
    ctx->pbdma_cb = pbdma_cb;
    ctx->tx_false_alarm_cb = tx_false_alarm_cb;
    ctx->deferred_cb = deferred_cb;
    ctx->extra_timer_user_data = NULL;
    ctx->extra_timer_cb = NULL;
    ctx->rx_fc_mode = PHY_FC_MODE_NONE;
    ctx->tx_short_ppdu = false;
    /* Attach interrupt. */
    cyg_drv_interrupt_create (LEON_ITC2_HIGH_PRIORITY_ITC1_IT,
                              LEON_ITC2_HIGH_PRIORITY_ITC1_IT_PRIORITY,
                              (cyg_addrword_t) ctx,
                              phy_isr,
                              phy_dsr,
                              &ctx->interrupt_handle,
                              &ctx->interrupt_context);
    cyg_drv_interrupt_attach (ctx->interrupt_handle);
    LEON_ITC2_CLEAR = PHY_ITC2_MASK;
    LEON_ITC2_LEVEL |= PHY_ITC2_MASK;
    LEON_ITC2_MASK |= PHY_ITC2_MASK;
    cyg_drv_interrupt_unmask (LEON_ITC2_HIGH_PRIORITY_ITC1_IT);
    /* Initialise hardware. */
    phy_clock_set_numerator (ctx, 1000000);
    PHY_PRATIC_IMMEDIATE_ACTION = PHY_PRATIC_ACTION__INIT_TX;
    PHY_PRATIC_IMMEDIATE_ACTION = PHY_PRATIC_ACTION__INIT_RX;
    PHY_DSPSS_COMMON_MODE = BF_FILL (PHY_DSPSS_COMMON_MODE,
                                     (USE_CRC_FC, 1),
                                     (USE_CRC_PB, 1),
                                     (CLK_150MHZ, 0));
    PHY_DSPSS_RX_FEC_PARAM = BF_FILL (PHY_DSPSS_RX_FEC_PARAM,
                                      (ME10DOI_MAX_IT, 9),
                                      (TCC_HALF_IT, 31),
                                      (TCC_DYN_STOP, 1),
                                      (TCC_BER_PERIOD, 1),
                                      (TCC_THRESHOLD, 0));
    PHY_DSPSS_RESYS_THRESHOLD = BF_FILL (PHY_DSPSS_RESYS_THRESHOLD,
                                         (NB_SYNCP_1, 4),
                                         (NB_SYNCP_2, 4));
    PHY_DSPSS_DETECT_PARAM_1 = BF_FILL (PHY_DSPSS_DETECT_PARAM_1,
                                        (LAMBDA, 25567),
                                        (GAMMA, 16712));
    PHY_DSPSS_DETECT_PARAM_2 = BF_FILL (PHY_DSPSS_DETECT_PARAM_2,
                                        (DMIN, 1536),
                                        (DMAX, 3264));
    PHY_DSPSS_DETECT_PARAM_3 = BF_FILL (PHY_DSPSS_DETECT_PARAM_3,
                                        (AFE_IN_BLOCK_EXP, (1 << 16) - 5),
                                        (USE_BAND_0, 1),
                                        (USE_BAND_1, 1));
    PHY_DSPSS_MAGIC_PARAM_1 = BF_FILL (PHY_DSPSS_MAGIC_PARAM_1,
                                       (TARGET_NRJ, 35),
                                       (CONVERGENCE_TOLERANCE, 3));
    PHY_DSPSS_MAGIC_PARAM_2 = BF_FILL (PHY_DSPSS_MAGIC_PARAM_2,
                                       (DIVERGENCE_TOLERANCE, 5));
    PHY_DSPSS_MAGIC_PARAM_3 = BF_FILL (PHY_DSPSS_MAGIC_PARAM_3,
                                       (MAX_GAIN, 60),
                                       (OVERFLOW_GAIN_RESET, 40),
                                       (AGC_MANUAL, 1),
                                       (AGC_MANUAL_START, 0));
    static const int mafadese_coef_filter_band0[26] = {
        -52, -42, 28, 22, -10, 26, 5, -11, 139, 171, -31, -65, 32,
        -42, -30, 52, -194, -348, -37, 102, -57, 21, 56, -97, 144, 434
    };
    static const int mafadese_coef_filter_band1[26] = {
        40, 28, -56, -13, -12, -26, 7, -37, 106, 148, -114, -59, -18,
        -85, 15, -101, 112, 337, -97, -121, -11, -139, 7, -143, 15, 434
    };
    uint i;
    volatile u32 *reg;
    reg = &PHY_DSPSS_MAFADESE_COEF_FILTER_BAND_0_0;
    for (i = 0; i < COUNT (mafadese_coef_filter_band0); i++)
        reg[i] = mafadese_coef_filter_band0[i];
    reg = &PHY_DSPSS_MAFADESE_COEF_FILTER_BAND_1_0;
    for (i = 0; i < COUNT (mafadese_coef_filter_band1); i++)
        reg[i] = mafadese_coef_filter_band1[i];
    /* Send RESYS program and offset table. */
    phy_resys_load (ctx);
    PHY_DSPSS_RESYS_PARAM = BF_FILL (PHY_DSPSS_RESYS_PARAM,
                                     (RESYS_COND, 0),
                                     (RESYS_ON, 1));
    /* Done. */
    return ctx;
}

static void
phy_set_robo_param (phy_t *ctx, u32 *tonemask, uint carrier_nb)
{
    static const uint n_copies_table[PHY_MOD_ROBO_NB] = { 4, 2, 5 };
    static const uint n_raw[PHY_MOD_ROBO_NB] = {
        520 * 8 * 2, 520 * 8 * 2, 136 * 8 * 2 };
    static volatile u32 * const robo_interleaver_1[PHY_MOD_ROBO_NB] = {
        &PHY_DSPSS_STD_ROBO_INTERLEAVER_1, &PHY_DSPSS_HS_ROBO_INTERLEAVER_1,
        &PHY_DSPSS_MINI_ROBO_INTERLEAVER_1 };
    static volatile u32 * const robo_interleaver_2[PHY_MOD_ROBO_NB] = {
        &PHY_DSPSS_STD_ROBO_INTERLEAVER_2, &PHY_DSPSS_HS_ROBO_INTERLEAVER_2,
        &PHY_DSPSS_MINI_ROBO_INTERLEAVER_2 };
    phy_mod_t i;
    for (i = PHY_MOD_ROBO; i < PHY_MOD_ROBO_NB; i++)
    {
        uint n_copies = n_copies_table[i];
        uint carrier_in_segment = carrier_nb / n_copies;
        uint carrier_nb_robo = carrier_in_segment * n_copies;
        uint bits_per_symbol = 2 * carrier_nb_robo;
        uint bits_in_segment = 2 * carrier_in_segment;
        uint bits_in_last_symbol = n_raw[i] % bits_per_symbol;
        uint bits_in_last_segment;
        if (bits_in_last_symbol == 0)
        {
            bits_in_last_symbol = bits_per_symbol;
            bits_in_last_segment = bits_in_segment;
        }
        else
        {
            bits_in_last_segment = bits_in_last_symbol - bits_in_segment
                * ((bits_in_last_symbol - 1) / bits_in_segment);
        }
        uint n_pad = bits_in_segment - bits_in_last_segment;
        *robo_interleaver_1[i] = BF_FILL (PHY_DSPSS_X_ROBO_INTERLEAVER_1,
                                          (NPAD, n_pad),
                                          (BITS_IN_SEGMENT, bits_in_segment));
        u32 cycle_shift;
        switch (i)
        {
        case PHY_MOD_ROBO:
            if (bits_in_last_symbol <= bits_in_segment)
                cycle_shift = BF_FILL (PHY_DSPSS_X_ROBO_INTERLEAVER_2,
                                       (CYCLE_SHIFT_0, 0),
                                       (CYCLE_SHIFT_1, 0),
                                       (CYCLE_SHIFT_2, 0),
                                       (CYCLE_SHIFT_3, 0));
            else if (bits_in_last_symbol <= 2 * bits_in_segment)
                cycle_shift = BF_FILL (PHY_DSPSS_X_ROBO_INTERLEAVER_2,
                                       (CYCLE_SHIFT_0, 0),
                                       (CYCLE_SHIFT_1, 0),
                                       (CYCLE_SHIFT_2, 1),
                                       (CYCLE_SHIFT_3, 1));
            else if (bits_in_last_symbol <= 3 * bits_in_segment)
                cycle_shift = BF_FILL (PHY_DSPSS_X_ROBO_INTERLEAVER_2,
                                       (CYCLE_SHIFT_0, 0),
                                       (CYCLE_SHIFT_1, 0),
                                       (CYCLE_SHIFT_2, 0),
                                       (CYCLE_SHIFT_3, 0));
            else
                cycle_shift = BF_FILL (PHY_DSPSS_X_ROBO_INTERLEAVER_2,
                                       (CYCLE_SHIFT_0, 0),
                                       (CYCLE_SHIFT_1, 1),
                                       (CYCLE_SHIFT_2, 2),
                                       (CYCLE_SHIFT_3, 3));
            break;
        case PHY_MOD_HS_ROBO:
            if (bits_in_last_symbol <= bits_in_segment)
                cycle_shift = BF_FILL (PHY_DSPSS_X_ROBO_INTERLEAVER_2,
                                       (CYCLE_SHIFT_0, 0),
                                       (CYCLE_SHIFT_1, 0));
            else
                cycle_shift = BF_FILL (PHY_DSPSS_X_ROBO_INTERLEAVER_2,
                                       (CYCLE_SHIFT_0, 0),
                                       (CYCLE_SHIFT_1, 1));
            break;
        case PHY_MOD_MINI_ROBO:
            if (bits_in_last_symbol <= 4 * bits_in_segment)
                cycle_shift = BF_FILL (PHY_DSPSS_X_ROBO_INTERLEAVER_2,
                                       (CYCLE_SHIFT_0, 0),
                                       (CYCLE_SHIFT_1, 0),
                                       (CYCLE_SHIFT_2, 0),
                                       (CYCLE_SHIFT_3, 0),
                                       (CYCLE_SHIFT_4, 0));
            else
                cycle_shift = BF_FILL (PHY_DSPSS_X_ROBO_INTERLEAVER_2,
                                       (CYCLE_SHIFT_0, 0),
                                       (CYCLE_SHIFT_1, 1),
                                       (CYCLE_SHIFT_2, 2),
                                       (CYCLE_SHIFT_3, 3),
                                       (CYCLE_SHIFT_4, 4));
            break;
        default:
            dbg_assert_default ();
        }
        *robo_interleaver_2[i] = cycle_shift
            | BF_SHIFT (PHY_DSPSS_X_ROBO_INTERLEAVER_2__MAX_CARRIER,
                        0x42c /* TODO */);
    }
}

void
phy_set_tonemask (phy_t *ctx, u32 *tonemask, uint carrier_nb)
{
    dbg_assert (ctx);
    dbg_assert_ptr (tonemask);
    dbg_assert (((u32) tonemask & 0x3) == 0);
    PHY_TRACE (SET_TONEMASK, carrier_nb);
    /* Send new tonemask. */
    phy_tmdma_desc_t desc;
    desc.next = NULL;
    desc.data = tonemask;
    desc.size_words = PHY_TONEMASK_WORDS;
    desc.mem_index = PHY_TMDMA_MEM_TONEMASK;
    desc.last = 1;
    desc.local_start_addr = 0;
    arch_write_buffer_flush ();
    PHY_DSPSS_TMD_DESC_ADDR = (u32) &desc;
    dbg_assert (!(PHY_DSPSS_TMD_CTRL & BF_MASK (PHY_DSPSS_TMD_CTRL__BUSY)));
    PHY_PRATIC_IMMEDIATE_ACTION = PHY_PRATIC_ACTION__TMD_START;
    /* XXX: Wait completion until TMDMA bug is fixed. */
    while (PHY_DSPSS_TMD_CTRL & BF_MASK (PHY_DSPSS_TMD_CTRL__BUSY))
        ;
    /* Set AV parameters. */
#define PHY_CARRIER_NB_10_FC 76
    PHY_DSPSS_HPAV_MASK = BF_FILL (PHY_DSPSS_HPAV_MASK,
                                   (NB_CARRIER, carrier_nb),
                                   (NB_CARRIER_10, PHY_CARRIER_NB_10_FC));
    /* Set HP 1.0 parameters. */
    PHY_DSPSS_HP10_MASK_0 = 0x0C060F01;
    PHY_DSPSS_HP10_MASK_1 = 0xC0000400;
    PHY_DSPSS_HP10_MASK_2 = 0x000C0001;
    PHY_DSPSS_HP10_MASK_3 = 0x0060001E;
    PHY_DSPSS_HP10_MASK_4 = 0x0000FFE0;
    PHY_DSPSS_HP10_FC_MASK_0 = 0x20006000;
    PHY_DSPSS_HP10_FC_MASK_1 = 0x000E0000;
    PHY_DSPSS_HP10_FC_MASK_2 = 0xFFF00060;
    /* Set ROBO parameters. */
    phy_set_robo_param (ctx, tonemask, carrier_nb);
    /* Create preamble. */
    PHY_PRATIC_IMMEDIATE_ACTION = PHY_PRATIC_ACTION__START_ACQU;
    PHY_PRATIC_IMMEDIATE_ACTION = PHY_PRATIC_ACTION__CREATE_PRE;
    while (PHY_DSPSS_TIME_CHAIN_INFO
           & BF_MASK (PHY_DSPSS_TIME_CHAIN_INFO__CREATION_IN_PROGRESS))
        ;
    PHY_PRATIC_IMMEDIATE_ACTION = PHY_PRATIC_ACTION__STOP_ACQU;
    /* Create PRS. */
    PHY_PRATIC_IMMEDIATE_ACTION = PHY_PRATIC_ACTION__START_ACQU;
    PHY_PRATIC_IMMEDIATE_ACTION = PHY_PRATIC_ACTION__CREATE_PRS;
    while (PHY_DSPSS_TIME_CHAIN_INFO
           & BF_MASK (PHY_DSPSS_TIME_CHAIN_INFO__CREATION_IN_PROGRESS))
        ;
    PHY_PRATIC_IMMEDIATE_ACTION = PHY_PRATIC_ACTION__STOP_ACQU;
}

void
phy_uninit (phy_t *ctx)
{
    dbg_assert (ctx);
    PHY_TRACE (UNINIT);
    /* Stop hardware. */
    PHY_PRATIC_TIMER_1_CTRL = 0;
    PHY_PRATIC_TIMER_2_CTRL = 0;
    PHY_PRATIC_TIMER_3_CTRL = 0;
    PHY_PRATIC_TIMER_4_CTRL = 0;
    PHY_PRATIC_TIMER_5_CTRL = 0;
    PHY_PRATIC_TIMER_6_CTRL = 0;
    PHY_PRATIC_TIMER_7_CTRL = 0;
    PHY_PRATIC_TIMER_8_CTRL = 0;
    PHY_PRATIC_TIMER_9_CTRL = 0;
    PHY_PRATIC_TIMER_10_CTRL = 0;
    PHY_PRATIC_IMMEDIATE_ACTION = PHY_PRATIC_ACTION__INIT_TX;
    PHY_PRATIC_IMMEDIATE_ACTION = PHY_PRATIC_ACTION__INIT_RX;
    /* Detach interrupt. */
    cyg_drv_interrupt_unmask (LEON_ITC2_HIGH_PRIORITY_ITC1_IT);
    cyg_drv_interrupt_detach (ctx->interrupt_handle);
    cyg_drv_interrupt_delete (ctx->interrupt_handle);
}

void
phy_reset (phy_t *ctx)
{
    dbg_assert (ctx);
    PHY_TRACE (RESET);
    /* TODO */
}

void
phy_set_tonemap (phy_t *ctx, uint tonemap_index, blk_t *tonemap)
{
    dbg_assert (ctx);
    dbg_assert (tonemap_index < 2);
    dbg_assert_ptr (tonemap);
    dbg_assert_ptr (tonemap->data);
    dbg_assert_ptr (tonemap->next);
    dbg_assert_ptr (tonemap->next->data);
    PHY_TRACE (SET_TONEMAP, tonemap_index, tonemap);
    /* Send new tonemap. */
    dbg_assert (PHY_TONEMAP_WORDS > BLK_SIZE / 4
                && PHY_TONEMAP_WORDS < 2 * BLK_SIZE / 4);
    phy_tmdma_desc_t *desc = (phy_tmdma_desc_t *) tonemap;
    desc->size_words = BLK_SIZE / 4;
    desc->mem_index = PHY_TMDMA_MEM_TONEMAP_0 + tonemap_index;
    desc->last = 0;
    desc->local_start_addr = 0;
    desc->next->size_words = PHY_TONEMAP_WORDS - BLK_SIZE / 4;
    desc->next->mem_index = PHY_TMDMA_MEM_TONEMAP_0 + tonemap_index;
    desc->next->last = 1;
    desc->next->local_start_addr = BLK_SIZE * 2; /* Two cells per byte. */
    arch_write_buffer_flush ();
    PHY_DSPSS_TMD_DESC_ADDR = (u32) desc;
    dbg_assert (!(PHY_DSPSS_TMD_CTRL & BF_MASK (PHY_DSPSS_TMD_CTRL__BUSY)));
    PHY_PRATIC_IMMEDIATE_ACTION = PHY_PRATIC_ACTION__TMD_START;
    /* XXX: Wait completion until TMDMA bug is fixed. */
    while (PHY_DSPSS_TMD_CTRL & BF_MASK (PHY_DSPSS_TMD_CTRL__BUSY))
        ;
}